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PDF ( 数据手册 , 数据表 ) SX1208

零件编号 SX1208
描述 Low Power Integrated UHF Transceiver
制造商 Semtech
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SX1208 数据手册, 描述, 功能
SX1208
WIRELESS, SENSING & TIMING
SX1208 Transceiver
Low Power Integrated UHF Transceiver
DATASHEET
RFIO
VBAT1&2
VR_ANA
VR_DIG
Power Distribution System
LNA

Single to
Mixers
Modulators
Differential
RC
Oscillator
GND
VR_PA
PA_BOOST
PA0
Ramp &
Control
PA1&2
Tank
Inductor
Loop
Filter
Division by
2, 4 or 6
Frac-N PLL
Synthesizer
XO
32 MHz
XTAL
RSSI
AFC
GND
RESET
SPI
RXTX
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
GENERAL DESCRIPTION
The SX1208 is a highly integrated RF transceiver capable of
operation from 290MHz to 510MHz, including the 315 and
434 MHz license-free ISM (Industry Scientific and Medical)
frequency bands. Its highly integrated architecture allows for
a minimum of external components whilst maintaining
maximum design flexibility. All major RF communication
parameters are programmable and most of them can be
dynamically set. The SX1208 offers the unique advantage
of programmable narrow-band and wide-band
communication modes without the need to modify external
components. The SX1208 is optimized for low power
consumption while offering high RF output power and
channelized operation. TrueRF™ technology enables a low-
cost external component count (elimination of the SAW
filter) whilst still satisfying ETSI and FCC regulations.
APPLICATIONS
Automated Meter Reading
Wireless Sensor Networks
Home and Building Automation
Wireless Alarm and Security Systems
Industrial Monitoring and Control
Smoke detectors
KEY PRODUCT FEATURES
High Sensitivity: down to -124 dBm at 600 bps
High Selectivity: 16-tap FIR Channel Filter
Bullet-proof front end: IIP3 = -18 dBm, IIP2 = +35 dBm,
80 dB Blocking Immunity, no Image Frequency response
Low current: Rx = 16 mA, 100nA register retention
Programmable Pout: -18 to +20 dBm in 1dB steps
Constant RF performance over voltage range of chip
FSK Bit rates up to 100 kbps
Fully integrated synthesizer with a resolution of 61 Hz
FSK, GFSK, MSK, GMSK and OOK modulations
Built-in Bit Synchronizer performing Clock Recovery
Incoming Sync Word Recognition
115 dB+ Dynamic Range RSSI
Automatic RF Sense with ultra-fast AFC
Packet engine with CRC, AES-128 and 66-byte FIFO
Built-in temperature sensor and Low Battery indicator
ORDERING INFORMATION
Part Number Package Delivery MOQ / Multiple
MARKETS
Europe: EN 300-220-1
North America: FCC Part 15.249
Korean Narrow bands
SX1208IMLTRT QFN24 Tape& Reel 3000 pieces
Pb-free, Halogen free, RoHS/WEEE compliant product
Temperature range: -40 to +85°C
Rev. 1 - March 2015
©2015 Semtech Corporation
Page 1
www.semtech.com







SX1208 pdf, 数据表
SX1208
WIRELESS, SENSING & TIMING
DATASHEET
This product datasheet contains a detailed description of the SX1208 performance and functionality. Please consult the
Semtech website for the latest updates or errata.
1. General Description
The SX1208 is a single-chip integrated circuit ideally suited for today's high performance ISM band RF applications. The
SX1208's advanced features set, including state of the art packet engine greatly simplifies system design whilst the high
level of integration reduces the external BOM to a handful of passive decoupling and matching components. It is intended
for use as high-performance, low-cost FSK and OOK RF transceiver for robust frequency agile, half-duplex bi-directional
RF links, and where stable and constant RF performance is required over the full operating range of the device down to
2.4V.
The SX1208 is intended for applications over 290 MHz to 510 MHz frequency range, including the 315 MHz and 434 MHz
ISM bands. Coupled with a link budget in excess of 142 dB, the advanced system features of the SX1208 include a 66 byte
TX/RX FIFO, configurable automatic packet handler, listen mode, temperature sensor and configurable DIOs which greatly
enhance system flexibility whilst at the same time significantly reducing MCU requirements.
The SX1208 complies with both ETSI and FCC regulatory requirements and is available in a 5 x 5 mm QFN 24 lead
package.
1.1. Simplified Block Diagram
VBAT1&2
VR_ANA
VR_DIG
Power Distribution System
RC
Oscillator
RFIO
LNA 
Single to
Mixers
Modulators
Differential
RESET
SPI
GND
VR_PA
PA_BOOST
PA0
Ramp &
Control
PA1&2
Tank
Inductor
Loop
Filter
Division by
2, 4 or 6
Frac-N PLL
Synthesizer
XO
32 MHz
RSSI
AFC
RXTX
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
Frequency Synthesis
Receiver Blocks
XTAL
GND
Transmitter Blocks
Control Blocks
Figure 1. Block Diagram
Primarily Analog
Primarily Digital
Rev. 1 - March 2015
©2015 Semtech Corporation
Page 8
www.semtech.com







SX1208 equivalent, schematic
SX1208
WIRELESS, SENSING & TIMING
DATASHEET
3. Chip Description
This section describes in depth the architecture of the SX1208 low-power, highly integrated transceiver.
3.1. Power Supply Strategy
The SX1208 employs an advanced power supply scheme, which provides stable operating characteristics over the full
temperature and voltage range of operation. This includes the full output power of +20dBm which is maintained from 2.4V
to 3.6 V.
The SX1208 can be powered from any low-noise voltage source via pins VBAT1 and VBAT2. Decoupling capacitors should
be connected, as suggested in the reference design, on VR_PA, VR_DIG and VR_ANA pins to ensure a correct operation
of the built-in voltage regulators.
3.2. Low Battery Detector
A low battery detector is also included allowing the generation of an interrupt signal in response to passing a
programmable threshold adjustable through the register RegLowBat. The interrupt signal can be mapped to any of the DIO
pins, through the programing of RegDioMapping.
3.3. Frequency Synthesis
The LO generation on the SX1208 is based on a state-of-the-art fractional-N PLL. The PLL is fully integrated with
automatic calibration.
3.3.1. Reference Oscillator
The crystal oscillator is the main timing reference of the SX1208. It is used as a reference for the frequency synthesizer
and as a clock for the digital processing.
The XO startup time, TS_OSC, depends on the actual XTAL being connected on pins XTA and XTB. When using the built-
in sequencer, the SX1208 optimizes the startup time and automatically triggers the PLL when the XO signal is stable. To
manually control the startup time, the user should either wait for TS_OSC max, or monitor the signal CLKOUT which will
only be made available on the output buffer when a stable XO oscillation is achieved.
An external clock can be used to replace the crystal oscillator, for instance a tight tolerance TCXO. To do so, bit 4 at
address 0x59 should be set to 1, and the external clock has to be provided on XTA (pin 4). XTB (pin 5) should be left open.
The peak-peak amplitude of the input signal must never exceed 1.8 V. Please consult your TCXO supplier for an
appropriate value of decoupling capacitor, CD.
XTA XTB
TCXO
32 MHz
OP
Vcc
GND
NC
Vcc
CD
Figure 4. TCXO Connection
Rev. 1 - March 2015
©2015 Semtech Corporation
Page 16
www.semtech.com










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