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PDF ( 数据手册 , 数据表 ) M40SZ100W

零件编号 M40SZ100W
描述 NVRAM supervisor
制造商 STMicroelectronics
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M40SZ100W 数据手册, 描述, 功能
M40SZ100W
3 V NVRAM supervisor for LPSRAM
16
1
SO16
Features
Convert low power SRAMs into NVRAMs
3 V operating voltage
Precision power monitoring and power
switching circuitry
Automatic write-protection when VCC is out-of-
tolerance
Choice of supply voltage and power-fail
deselect voltage:
– VCC = 2.7 to 3.6 V; 2.55 V VPFD 2.70 V
Reset output (RST) for power on reset
1.25 V reference (for PFI/PFO)
Less than 15 ns chip enable access
propagation delay
Battery low pin (BL)
RoHS compliant
– Lead-free second level interconnect
Datasheet - production data
Description
The M40SZ100W NVRAM controller is a self-
contained device which converts a standard low-
power SRAM into a non-volatile memory. A
precision voltage reference and comparator
monitors the VCC input for an out-of-tolerance
condition.
When an invalid VCC condition occurs, the
conditioned chip enable output (ECON) is forced
inactive to write protect the stored data in the
SRAM. During a power failure, the SRAM is
switched from the VCC pin to the external battery
to provide the energy required for data retention.
On a subsequent power-up, the SRAM remains
write-protected until a valid power condition
returns.
December 2013
This is information on a product in full production.
DocID007528 Rev 4
1/20
www.st.com







M40SZ100W pdf, 数据表
Operation
2 Operation
M40SZ100W
The M40SZ100W, as shown in Figure 4 on page 7, can control one (two, if placed in
parallel) standard low-power SRAM. This SRAM must be configured to have the chip enable
input disable all other input signals. Most slow, low-power SRAMs are configured like this,
however many fast SRAMs are not. During normal operating conditions, the conditioned
chip enable (ECON) output pin follows the chip enable (E) input pin with timing shown in
Table 2 on page 10. An internal switch connects VCC to VOUT. This switch has a voltage
drop of less than 0.3 V (IOUT1).
When VCC degrades during a power failure, ECON is forced inactive independent of E. In
this situation, the SRAM is unconditionally write protected as VCC falls below an out-of-
tolerance threshold (VPFD). For the M40SZ100W the power fail detection value associated
with VPFD is shown in Table 7 on page 16.
If chip enable access is in progress during a power fail detection, that memory cycle
continues to completion before the memory is write protected. If the memory cycle is not
terminated within time tWPT, ECON is unconditionally driven high, write protecting the SRAM.
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the SRAM's contents. At voltages below VPFD (min), the
user can be assured the memory will be write protected within the Write Protect Time (tWPT)
provided the VCC fall time does not exceed tF (see Table 2 on page 10).
As VCC continues to degrade, the internal switch disconnects VCC and connects the internal
battery to VOUT. This occurs at the switchover voltage (VSO). Below the VSO, the battery
provides a voltage VOHB to the SRAM and can supply current IOUT2 (see Table 7 on
page 16).
When VCC rises above VSO, VOUT is switched back to the supply voltage. Output ECON is
held inactive for tCER (120 ms maximum) after the power supply has reached VPFD,
independent of the E input, to allow for processor stabilization (see Figure 6 on page 10).
2.1
Caution:
Data retention lifetime calculation
Most low power SRAMs on the market today can be used with the M40SZ100W NVRAM
controller. There are, however some criteria which should be used in making the final choice
of which SRAM to use. The SRAM must be designed in a way where the chip enable input
disables all other inputs to the SRAM. This allows inputs to the M40SZ100W and SRAMs to
be “Don't care” once VCC falls below VPFD(min) (see Figure 5 on page 9). The SRAM should
also guarantee data retention down to VCC = 2.0 V. The chip enable access time must be
sufficient to meet the system needs with the chip enable propagation delays included.
If data retention lifetime is a critical parameter for the system, it is important to review the
data retention current specifications for the particular SRAMs being evaluated. Most SRAMs
specify a data retention current at 3.0 V. Manufacturers generally specify a typical condition
for room temperature along with a worst case condition (generally at elevated
temperatures). The system level requirements will determine the choice of which value to
use. The data retention current value of the SRAMs can then be added to the ICCDR value of
the M40SZ100W to determine the total current requirements for data retention.
Take care to avoid inadvertent discharge through VOUT and ECON after battery has been
attached.
8/20 DocID007528 Rev 4







M40SZ100W equivalent, schematic
DC and AC parameters
M40SZ100W
Sym
Table 7. DC characteristics
Parameter
Test condition(1)
Min
Typ
Max Unit
ICC Supply current
ICCDR Data retention mode current(2)
ILI(3)
Input leakage current
Input leakage current (PFI)
ILO(4) Output leakage current
IOUT1(5) VOUT current (active)
IOUT2 VOUT current (battery backup)
VBAT Battery voltage
VIH Input high voltage
VIL
VOH
VOHB
Input low voltage
Output high voltage(6)
VOH battery backup(7)
Output low voltage
VOL Output low voltage (open
drain)(8)
VPFD
VPFI
Power-fail deselect voltage
PFI input threshold
PFI hysteresis
VSO
Battery backup switchover
voltage
Outputs open
0 V VIN VCC
0 V VOUT VCC
VOUT > VCC – 0.3
VOUT > VBAT – 0.3
IOH = –1.0 mA
IOUT2 = –1.0 μA
IOL = 3.0 mA
–25
2.5
0.7VCC
–0.3
2.4
2.5
0.5 mA
50 200 nA
±1 μA
2 25 nA
±1 μA
100 mA
100 μA
3.0 3.5(6) V
VCC + 0.3
0.3VCC
V
V
V
2.9 3.5 V
0.4 V
IOL = 10 mA
0.4 V
VCC = 3 V
PFI rising
2.55
1.225
2.60
1.250
20
2.70
1.275
70
V
V
mV
2.5 V
1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 2.7 to 3.6 V (except where noted).
2. Measured with VOUT and ECON open.
3. RSTIN internally pulled-up to VCC through 100 kresistor.
4. Outputs deselected.
5. External SRAM must match SUPERVISOR chip VCC specification.
6. For PFO pin (CMOS).
7.
lCehaikpaegneacbulerreonuttspuwtil(lEreCdOuNc)ecabnatotenrlyy
sustain
life.
CMOS
leakage
currents
in
the
battery
backup
mode.
Higher
8. For RST & BL pins (open drain).
16/20
DocID007528 Rev 4










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