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PDF ( 数据手册 , 数据表 ) W632GU6KB

零件编号 W632GU6KB
描述 16M x 8-BANKS x 16-BIT DDR3L SDRAM
制造商 Winbond
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W632GU6KB 数据手册, 描述, 功能
W632GU6KB
16M 8 BANKS 16 BIT DDR3L SDRAM
Table of Contents-
1. GENERAL DESCRIPTION ...................................................................................................................5
2. FEATURES ...........................................................................................................................................5
3. ORDER INFORMATION .......................................................................................................................6
4. KEY PARAMETERS .............................................................................................................................7
5. BALL CONFIGURATION ......................................................................................................................8
6. BALL DESCRIPTION............................................................................................................................9
7. BLOCK DIAGRAM ..............................................................................................................................11
8. FUNCTIONAL DESCRIPTION............................................................................................................12
8.1 Basic Functionality ..............................................................................................................................12
8.2 RESET and Initialization Procedure ....................................................................................................12
8.2.1
Power-up Initialization Sequence .....................................................................................12
8.2.2
Reset Initialization with Stable Power ..............................................................................14
8.3 Programming the Mode Registers.......................................................................................................15
8.3.1
Mode Register MR0 .........................................................................................................17
8.3.1.1
Burst Length, Type and Order ................................................................................18
8.3.1.2
CAS Latency...........................................................................................................18
8.3.1.3
Test Mode...............................................................................................................19
8.3.1.4
DLL Reset...............................................................................................................19
8.3.1.5
Write Recovery .......................................................................................................19
8.3.1.6
Precharge PD DLL .................................................................................................19
8.3.2
Mode Register MR1 .........................................................................................................20
8.3.2.1
DLL Enable/Disable................................................................................................20
8.3.2.2
Output Driver Impedance Control ...........................................................................21
8.3.2.3
ODT RTT Values ....................................................................................................21
8.3.2.4
Additive Latency (AL) .............................................................................................21
8.3.2.5
Write leveling ..........................................................................................................21
8.3.2.6
Output Disable........................................................................................................21
8.3.3
Mode Register MR2 .........................................................................................................22
8.3.3.1
Partial Array Self Refresh (PASR) ..........................................................................23
8.3.3.2
CAS Write Latency (CWL) ......................................................................................23
8.3.3.3
Auto Self Refresh (ASR) and Self Refresh Temperature (SRT) .............................23
8.3.3.4
Dynamic ODT (Rtt_WR) .........................................................................................23
8.3.4
Mode Register MR3 .........................................................................................................24
8.3.4.1
Multi Purpose Register (MPR) ................................................................................24
8.4 No OPeration (NOP) Command..........................................................................................................25
8.5 Deselect Command.............................................................................................................................25
8.6 DLL-off Mode ......................................................................................................................................25
8.7 DLL on/off switching procedure...........................................................................................................26
8.7.1
DLL onto DLL offProcedure ..........................................................................26
8.7.2
DLL offto DLL onProcedure ..........................................................................27
8.8 Input clock frequency change..............................................................................................................28
8.8.1
Frequency change during Self-Refresh............................................................................28
8.8.2
Frequency change during Precharge Power-down ..........................................................28
8.9 Write Leveling .....................................................................................................................................30
Publication Release Date: Jan. 20, 2015
Revision: A06
-1-







W632GU6KB pdf, 数据表
W632GU6KB
5. BALL CONFIGURATION
1
2
3
45
6
7
8
9
VDDQ DQU5 DQU7
A
DQU4 VDDQ VSS
VSSQ VDD
VSS
VDDQ DQU3 DQU1
B
C
DQSU# DQU6 VSSQ
DQSU DQU2 VDDQ
VSSQ VDDQ DMU
D
DQU0 VSSQ VDD
VSS VSSQ DQL0
VDDQ DQL2 DQSL
E
F
DML VSSQ VDDQ
DQL1 DQL3 VSSQ
VSSQ DQL6 DQSL#
G
VDD
VSS VSSQ
VREFDQ VDDQ DQL4
H
DQL7 DQL5 VDDQ
NC VSS RAS#
J
CK VSS NC
ODT VDD CAS#
K
CK#
VDD
CKE
NC
CS#
WE#
L
A10/AP ZQ
NC
VSS BA0 BA2
VDD
A3
A0
M NC VREFCA VSS
N
A12/BC# BA1
VDD
VSS
A5
A2
VDD
A7
A9
VSS RESET# A13
P
R
T
A1 A4 VSS
A11 A6 VDD
NC A8 VSS
Publication Release Date: Jan. 20, 2015
Revision: A06
-8-







W632GU6KB equivalent, schematic
W632GU6KB
The MRS command to Non-MRS command delay, tMOD is required for the DRAM to update the
features, except DLL reset, and is the minimum time required from a MRS command to a non-MRS
command excluding NOP and DES shown in Figure 4.
CK#
CK
Command
T0
VALID
T1
VALID
T2
VALID
Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Tb1
MRS
NOP/DES
NOP/DES
NOP/DES
NOP/DES
NOP/DES
VALID
Tb2
VALID
Address
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
CKE
Settings
Old settings
Rtt_Nom ENABLED prior and/or after MRS command
ODT
VALID
VALID
ODTLoff+1
Updating Settings
tMOD
New Settings
VALID
Rtt_Nom DISABLED prior and/or after MRS command
ODT
VALID
VALID
VALID
VALID
VALID
VALID
VALID
Figure 4 tMOD Timing
VALID
VALID
VALID
TIME BREAK
VALID
DON'T CARE
The mode register contents can be changed using the same command and timing requirements
during normal operation as long as the DRAM is in idle state, i.e., all banks are in the precharged state
with tRP satisfied, all data bursts are completed and CKE is high prior to writing into the mode register.
If the Rtt_Nom Feature is enabled in the Mode Register prior and/or after a MRS command, the ODT
signal must continuously be registered LOW ensuring RTT is in an off state prior to the MRS
command. The ODT signal may be registered high after tMOD has expired. If the Rtt_Nom feature is
disabled in the Mode Register prior and after a MRS command, the ODT signal can be registered
either LOW or HIGH before, during and after the MRS command. The mode registers are divided into
various fields depending on the functionality and/or modes.
- 16 -
Publication Release Date: Jan. 20, 2015
Revision: A06










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