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PDF ( 数据手册 , 数据表 ) L9230-DIE1

零件编号 L9230-DIE1
描述 SPI CONTROLLED H-BRIDGE
制造商 STMicroelectronics
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L9230-DIE1 数据手册, 描述, 功能
L9230
s OPERATING SUPPLY VOLTAGE 5V TO 28V
s TYPICAL RDSon = 150 mFOR EACH
OUTPUT TRANSISTOR (AT 25°C)
s CONTINOUS DC LOAD CURRENT 5A
(Tcase < 100 °C)
s OUTPUT CURRENT LIMITATION AT TYP. 6A
s SHORT CIRCUIT SHUT DOWN FOR OUTPUT
CURRENTS OVER 8A
s LOGIC- INPUTS TTL/CMOS-COMPATIBLE
s OPERATING-FREQUENCY UP TO 30 kHz
s OVER TEMPERATURE PROTECTION
s SHORT CIRCUIT PROTECTION
s UNDERVOLTAGE DISABLE FUNCTION
s DIAGNOSTIC BY SPI OR STATUS-FLAG
(CONFIGURABLE)
s ENABLE AND DISABLE INPUT
s SO20 POWER PACKAGE
DESCRIPTION
The L9230 is an SPI controlled H-Bridge, designed
for the control of DC and stepper motors in safety crit-
ical applications and under extreme environmental
conditions.
SPI CONTROLLED H-BRIDGE
PRELIMINARY DATA
PowerSO20
BARE-DIE
ORDERING NUMBERS:
L9230
L9230-DIE1
The H-Bridge is protected against over temperature
and short circuits and has an under voltage lockout
for all the supply voltages ”VS” (Main DC power sup-
ply). All malfunctions cause the output stages to go
tristate.
The H-Bridge contains integrated free-wheel diodes.
In case of free-wheeling condition, the lowside tran-
sistor is switched on in parallel of its diode to reduce
the current injected into the substrate.
Switching in parallel is only allowed, if the voltage-
level of the according output-stage is below the
ground-level.In this case it must be ensured, that the
upper transistor is switched off.
BLOCK DIAGRAM
UNDERVOLTAGE
VS
INTERNAL 5V
SUPPLY
VS
IN1
IN2
DI
EN
DMS
SF/SCK
SS
SI
SO
LOGIC
GATE CONTROL
1
GATE CONTROL
2
OVER
TEMPERATURE
MAXIMUM
CURRENT
LIMITATION
OVERCURRENT
HIGH-SIDE
OVERCURRENT
LOW-SIDE
OUT1
OUT2
GND
D01AT470A
March 2003
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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L9230-DIE1 pdf, 数据表
L9230
ELECTRICAL CHARACTERISTICS (continued)
SPI INTERFACE
The timing of L9230 is defined as follows:
- The change at output (SO) is forced by the rising edge of the SCK signal.
- The input signal (SI) is taken over on the falling edge of the SCK signal.
- SS = active without any clocks at SCK is not allowed
- The data received during a writing access is taken over into the internal registers on the rising edge of the SS
signal, if exactly 16 SPI clocks have been counted during SS = active.
Figure 6.
SS
11 2
10
1
9
38
SCK
SO
SI
12
47
tristate
Bit (n-3) Bit (n-4)...1 Bit 0; LSB
56
MSB IN Bit (n-2) Bit (n-3) Bit (n-4)...1 LSB IN
n = 16
ELECTRICAL CHARACTERISTCS ( continued)
Symbol
Parameter
Input SCK (SPI clock input 4.5V < DMS < 5.5V)
VSCKL Low Level
VSCKH High Level
Test Condition
VSCK Hysteresis
CSCK Input Capacity
Min. Typ. Max. Unit
1V
2V
0.1 0.4 V
10 pF
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L9230-DIE1 equivalent, schematic
L9230
SPI Communication
Figure 9. Reading access / 8 bit
SS
SI
SPI INSTRUCTION
MSB
XXXX XXXX
VERIFICATION BYTE
DATA/8 BIT
SO
MSB
MSB
D01AT480
SPI Instruction
The uppermost 2 bit of the instruction byte contains the chipadress. The individual chipadress is a mask-option
and must be defined in accordance to the SPI-Members sharing on SS line.
SPI Instruction-Format
MSB
76
00
5
INSTR4
4
INSTR3
3
INSTR2
2
INSTR1
1
INSR0
0
INSW
Bit Name
Description
7,6
CPAD1,0
Chip Adress (has to be ‘0’, ‘0’)
5-1
INSTR (4-0)
SPI instruction (encoding)
0
INSW
Don‘t care
SPI Instruction-Bytes
SPI Instruction
bit 7,6
CPAD1,0
Encoding
bit 5,4,3,2,1
INSTR(4...0)
Bit 0
Description
RD_IDENT
00 00000
0 read identifier
RD_VERSION
00 00001
1 read version
RD_DIA
00 00100
all others
1 read DIA_REG
no function
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