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PDF ( 数据手册 , 数据表 ) SX1238

零件编号 SX1238
描述 Fully Integrated Transceiver
制造商 Semtech
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SX1238 数据手册, 描述, 功能
WIRELESS, SENSING & TIMING
SX1238 - Fully Integrated Transceiver with +27dBm TX Power
SX1238
DATASHEET
VDD2 RXEN MODE RX RFI
PREAMP
VBAT1&2
VR_ANA
VR_DIG
LNA
Power Distribution System
Single to
Differential
Mixers
RC
Oscillator
ANT
IND
PA
PA0
Ramp &
Control
VDD1 PAout PDET TXEN TX RFO VR_PA
Preamp/PA
Tank
Inductor
Loop
Filter
Division by
2,4, or 6
Frac-N PLL
Synthesizer
XO
32 MHz
RSSI AFC
XTAL
GND
Frequency Synthesis
Transmitter Blocks
Receive Blocks
Control Blocks
Primary Analog
Primary Digital
RESET
SPI
RXTX
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
GENERAL DESCRIPTION
The SX1238 is a fully integrated ISM band transceiver
optimized for use in the (FCC Part 15) 915 MHz band in the
US and 868 MHz band in Europe with a minimum of
external components. It offers a combination of high link
budget and low current consumption in all operating modes.
The 150 dB link budget is achieved by a low noise CMOS
receiver front end and up to +27 dBm of transmit output
power. This is made possible by a fully integrated front end
consisting of a TR Switch, LNA and efficient PA. This makes
SX1238 ideal for applications requiring extended range,
high link budget, or operation in the presence of high
interference.
The Low-IF architecture of the SX1238 sees fast transceiver
start times and demodulation predicated towards low
modulation index and Gaussian filtered spectrally efficient
modulation formats.
APPLICATIONS
Automated Meter Reading
Wireless Sensor Networks
Home and Building Automation
Wireless Alarm and Security Systems
Industrial Monitoring and Control
KEY PRODUCT FEATURES
+27 dBm - 500 mW RF output power
+27 dBm high efficiency PA
Programmable bit rate up to 300kbps
High sensitivity: -124 dBm at 1.2 kbps
863 - 870 MHz and 902 - 928 MHz
80 dB blocking Immunity
Low current, 100nA register retention
Fully integrated synthesizer with a resolution of 61 Hz
FSK, GFSK, MSK, GMSK and OOK modulations
Built-in bit synchronizer performing clock recovery
Sync word recognition
Preamble detection
115 dB+ dynamic range RSSI
Automatic RF sense with ultra-fast AFC
Packet engine up to 64 bytes with CRC
Built-in temperature sensor and low battery indicator
ORDERING INFORMATION
Part Number
SX1238IMLTRT
Delivery
Tape & Reel
MOQ / Multiple
3000 pieces
MLPQ 40 Package - Operating Range [-40;+85°C]
Pb-free, Halogen free, RoHS/WEEE compliant product
SX1238 Rev.2, June 2014
©2014 Semtech Corp.
Page 1
www.semtech.com







SX1238 pdf, 数据表
WIRELESS, SENSING & TIMING
SX1238
High Power Transceiver IC
DATASHEET
1.3. Pin Description
Table 1 SX1238 Pinouts
Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Name
GROUND
VDD2
RX
VDD1
MODE
RXEN
TXEN
TX
RXTX
RFO
RFI
GND
VR_PA
VBAT1
GND
VR_ANA
VR_DIG
XTA
XTB
RESET
NC
DIO0
DIO1/DCLK
DIO2/DATA
DIO3
DIO4
DIO5
VBAT2
GND
SCK
MISO
SX1238 Rev.2, June 2014
©2014 Semtech Corp.
Type
-
-
O
-
I
I
I
I
O
O
I
-
-
-
-
-
-
I/O
I/O
I/O
-
I/O
I/O
I/O
I/O
I/O
I/O
-
-
I
O
Description
Exposed ground pad
LNA Voltage Supply
LNA output (DC short to GND, use DC block)
Driver stage Voltage Supply
Selects High or Low LNA Gain
Enables Receive Mode
Enables Transmit Mode
PA Input (DC short to GND, use DC block)
Rx/Tx switch control: high in Tx
RF output (connects to TX)
RF input (connects to RX LNA output)
Ground
Regulated supply for the PA
Supply voltage
Ground
Regulated supply voltage for analogue circuitry
Regulated supply voltage for digital blocks
XTAL connection or TCXO input
XTAL connection
Reset trigger input
No Connection
Digital I/O, software configured
Digital I/O, software configured
Digital I/O, software configured
Digital I/O, software configured
Digital I/O, software configured
Digital I/O, software configured
Supply voltage
Ground
SPI Clock input
SPI Data output
Page 8
www.semtech.com







SX1238 equivalent, schematic
WIRELESS, SENSING & TIMING
SX1238
High Power Transceiver IC
DATASHEET
3. Chip Description
This section describes in depth the architecture of the SX1238 low-power, highly integrated transceiver. The following
figure shows a simplified block diagram of the SX1238.
RX EN VDD2 MODE
LNA1
ANT
IND
PA2
RX RFI
PA0
VBAT1 VBAT2 VR_ANA VR_DIG
LNA2
Single to diff
POWER DISTRIBUTION SYSTEM
M IX ER
ADC_TOP
ADCI
(sigma-delta)
ADCQ
(sigma-delta)
PLL
Decimation mixing
RX Chain
filtering
RSSI
control
AFC
RXTX
NSS
M ISO
MOSI
SCK
IRQ (5:0)
PA_REG
TX EN PAout VDD1
TX RFO VR_PA
Tx DAC
XTAL OSC
RX OSC
XTA XTB
filtering
TX Chain
GND RESET GND
Figure 5. Simplified SX1238 Block Schematic Diagram
SX1238 is a half-duplex, low-IF transceiver. Here the received RF signal at the ANT port is amplified by LNA1 when RXEN
is enabled. The MODE selects high or low LNA1 gain. LNA1 output passes through an external filter/matching network,
then enters LNA2. Both LNA1 and LNA2 inputs are single ended to minimize the external BoM and for ease of design.
Following LNA2 output, the conversion to differential is made internally to improve the second order linearity and harmonic
rejection. The signal is then down-converted to in-phase (I) and quadrature (Q) components at the intermediate frequency
(IF) by the mixer stage. A pair of sigma delta ADCs then perform data conversion, with all subsequent signal processing
and demodulation performed in the digital domain. The digital state machine also controls the automatic frequency
correction (AFC), received signal strength indicator (RSSI) and automatic gain control (AGC). It also features the higher-
level packet and protocol level functionality of the top level sequencer.
In the receiver operating mode two states of functionality are defined. Upon initial transition to receiver operating mode the
receiver is in the ‘receiver-enabled’ state. In this state the receiver awaits for either the user defined valid preamble or RSSI
detection criterion to be fulfilled. Once met the receiver enters ‘receiver-active’ state. In this second state the received
signal is processed by the packet engine and top level sequencer.
The frequency synthesizer generates the local oscillator (LO) frequency for both receiver and transmitter. The PLL is
optimized for user-transparent low lock time and fast auto-calibrating operation. In transmission, frequency modulation is
performed digitally within the PLL bandwidth. It also features optional pre-filtering of the bit stream to improve spectral
purity.
The SX1238 features a pair of RF power amplifiers. The first, PA0, connected to RFO, passes through a filter/bias network
then enters PA2 input connected to TX. PA2 output is connected to the T/R switch and can deliver up to +27 dBm to the
ANT port directly into a 50 Ohm load when the TXEN is enabled. The PDET provides an analog DC voltage proportional to
PA2 output power.
SX1238 Rev.2, June 2014
©2014 Semtech Corp.
Page 16
www.semtech.com










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