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PDF ( 数据手册 , 数据表 ) M301N2F8TFP

零件编号 M301N2F8TFP
描述 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
制造商 Renesas
LOGO Renesas LOGO 


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M301N2F8TFP 数据手册, 描述, 功能
M16C/1N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
REJ03B0002-0100Z
Rev.1.00
2004.10.20
1. Overview
The M16C/1N group consists of single-chip microcomputers that use high-performance silicon gate CMOS
processes and have a on-chip M16C/60 series CPU core. The microcomputers are housed in 48-pin plastic
mold QFP package. These single-chip microcomputers have both high function instructions and high in-
struction efficiency and feature a one-megabyte address space and the capability to execute instructions at
high speed.
1.1 Applications
Automotive and industrial control systems, other automobile, other
Rev.1.00 Oct 20, 2004 page 1 of 29
REJ03B0002-0100Z







M301N2F8TFP pdf, 数据表
M16C/1N Group
2. Central Processing Unit (CPU)
2.3 Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7 Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8 Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1 Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2 Debug Flag (D Flag)
This flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.
2.8.3 Zero Flag (Z Flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
2.8.4 Sign Flag (S Flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.
2.8.5 Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is “0”; register bank 1 is selected when this flag is “1”.
2.8.6 Overflow Flag (O Flag)
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
2.8.7 Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I flag
is set to “0” when the interrupt request is accepted.
2.8.8 Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is set to “0” when a hardware interrupt request is accepted or an INT instruction for software
interrupt Nos. 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from
level 0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt request is enabled.
2.8.10 Reserved Area
When white to this bit, write “0”. When read, its content is indeterminate.
Rev.1.00 Oct 20, 2004 page 8 of 29
REJ03B0002-0100Z







M301N2F8TFP equivalent, schematic
M16C/1N Group
4. Special Function Registers (SFR)
Address
028016
028116
028216
028316
028416
028516
028616
028716
028816
028916
028A16
028B16
028C16
028D16
028E16
028F16
029016
029116
029216
029316
029416
029516
029616
029716
029816
029916
029A16
029B16
029C16
029D16
029E16
029F16
02A016
02A116
02A216
02A316
02A416
02A516
02A616
02A716
02A816
02A916
02AA16
02AB16
02AC16
02AD16
02AE16
02AF16
02B016
02B116
02B216
02B316
02B416
02B516
02B616
02B716
02B816
02B916
02BA16
02BB16
02BC16
02BD16
02BE16
02BF16
Register
CAN0 slot 2: Identifier / DLC
CAN0 slot 2: Data Field
CAN0 slot 2: Time Stamp
CAN0 slot 3: Identifier / DLC
CAN0 slot 3: Data Field
CAN0 slot 3: Time Stamp
CAN0 slot 4: Identifier / DLC
CAN0 slot 4: Data Field
CAN0 slot 4: Time Stamp
CAN0 slot 5: Identifier / DLC
CAN0 slot 5: Data Field
CAN0 slot 5: Time Stamp
Symbol
After reset
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
Note 1: Location in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
X : Undefined
Rev.1.00 Oct 20, 2004 page 16 of 29
REJ03B0002-0100Z










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