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PDF ( 数据手册 , 数据表 ) 7512

零件编号 7512
描述 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
制造商 Renesas
LOGO Renesas LOGO 


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7512 数据手册, 描述, 功能
7512 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
REJ03B0122-0101
Rev.1.01
Feb 18, 2005
DESCRIPTION
The 7512 Group is the 8-bit microcomputer based on the 740 fam-
ily core technology.
The 7512 Group is designed for battery-pack and includes serial
interface functions, 8-bit timer, A/D converter, current integrator
and I2C-BUS interface.
FEATURES
qBasic machine-language instructions ...................................... 71
qMinimum instruction execution time .................................. 1.0 µs
(at 4 MHz oscillation frequency)
qMemory size
Flash memory .................................................. 36 K to 52 Kbytes
RAM ............................................................... 1.0 K to 1.5 Kbytes
qProgrammable input/output ports ............................................ 36
qInterrupts ................................................. 19 sources, 16 vectors
qTimers ............................................................................. 8-bit 4
qSerial interface
Serial I/O1 .......... 8-bit 1 (UART or Clock-synchronized)
Serial I/O2 .......................... 8-bit 1(Clock-synchronized)
qMulti-master I2C-BUS interface (option) ...................... 1 channel
qPWM ............................................................................... 8-bit 1
qA/D converter ............................................. 10-bit 10 channels
qCurrent integrator ......................................................... 1 channel
qOver current detector ................................................... 1 channel
qEasy thermal sensor .................................................... 1 channel
qWatchdog timer ............................................................ 16-bit 1
qClock generating circuit ..................................... Built-in 4 circuits
(high-speed RC oscillator and 32kHz RC oscillator, or connect to
external ceramic resonator or quartz-crystal oscillator)
qPower source voltage ............................................ 2.45 to 2.55 V
qPower dissipation
In high-speed mode ...................................................... 3.75 mW
(at 4 MHz oscillation frequency, at 2.5 V power source voltage)
In low-speed mode ........................................................ 1.05 mW
(at 32 kHz oscillation frequency, at 2.5 V power source voltage)
qOperating temperature range .................................... –20 to 85°C
APPLICATION
Battery-Pack, etc.
PIN CONFIGURATION (TOP VIEW)
P33/AN3
P32/AN2
P31/AN1
P30/AN0
ADVSS
ADVRED
VCC
AVCC
AVSS
ISENS0
ISENS1
DFETCNT/P45
37
38
39
40
41
42
43
44
45
46
47
48
M37512FCHP
24 P12/(LED2)
23 P13/(LED3)
22 P14/(LED4)
21 P15/(LED5)
20 P16/(LED6)
19 P17/(LED7)
18 VSS
17 XOUT
16 XIN
15 RESET
14 P20/XCOUT
13 P21/XCIN
Fig. 1 M37512FCHP pin configuration
Feb 18, 2005 page 1 of 85
REJ03B0122-0101
Package type : 48P6Q-A







7512 pdf, 数据表
7512 Group
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit, etc.
The CPU mode register is allocated at address 003B16.
b7
Fig. 6 Structure of CPU mode register
b0
CPU mode register
(CPUM : address 003B16)
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1:
1 0:
Not available
1 1:
Stack page selection bit
0 : 0 page
1 : 1 page
Clock source switch bit
0 : Built-in high speed oscillating function
1 : XCINXCOUT oscillation function
Port XC switch bit
0 : I/O port function (stop oscillation)
1 : XCINXCOUT oscillation function
Main clock (XINXOUT) stop bit
0 : Oscillation
1 : Stopped
Main clock division ratio selection bits
b7 b6
0 0 : φ = f(XIN)/2 (high-speed mode)
0 1 : φ = f(XIN)/8 (middle-speed mode)
1 0 : φ = f(XIN)/2 (low-speed mode)
1 1 : Not available
Note : All bits in this register are protected by protect mode.
Feb 18, 2005 page 8 of 85
REJ03B0122-0101







7512 equivalent, schematic
7512 Group
Table 6 Interrupt vector addresses and priority
Interrupt Source
Reset (Note 2)
INT0
Priority
1
2
SCL, SDA
INT1
INT2
3
4
5
Vector Addresses (Note 1)
High
Low
FFFD16
FFFC16
FFFB16
FFFA16
FFF916
FFF816
FFF716
FFF616
FFF516
FFF416
Interrupt Request
Generating Conditions
At reset
At detection of either rising or
falling edge of INT0 input
At detection of either rising or
falling edge of SCL or SDA input
At detection of either rising or
falling edge of INT1 input
At detection of either rising or
falling edge of INT2 input
Remarks
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
INT3
Serial I/O2
I2C
Timer X
Timer Y
Timer 1
Timer 2
Serial I/O1
reception
Serial I/O1
Transmission
Over current
detection
6 FFF316
7 FFF116
8 FFEF16
9 FFED16
10 FFEB16
11 FFE916
12 FFE716
13 FFE516
CNTR0
CNTR1
A/D converter
Current integration
BRK instruction
14
15
16
17
FFE316
FFE116
FFDF16
FFDD16
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
At detection of either rising or
falling edge of INT3 input
At completion of serial I/O2 data
reception / transmission
At completion of data transfer
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
At completion of serial I/O1 data
reception
At completion of serial I/O1
transfer shift or when transmis-
sion buffer is empty
At discharge short current is de-
tected, at discharge over current
is detected, at wake up current
is detected, or at charge over
current is detected.
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of CNTR1 input
At completion of A/D conversion
At end of current integration
period, or at end of calibration
At BRK instruction execution
External interrupt
(active edge selectable)
Valid when serial I/O2 is selected
STP release timer underflow
Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
Valid when discharge short current
detector or discharge current
detector, or wake up current
detector, or charge over current
detector is selected.
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when current integrator is
selected
Non-maskable software interrupt
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Feb 18, 2005 page 16 of 85
REJ03B0122-0101










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