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PDF ( 数据手册 , 数据表 ) M95080-A145

零件编号 M95080-A145
描述 Automotive 8-Kbit serial SPI bus EEPROMs
制造商 STMicroelectronics
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M95080-A145 数据手册, 描述, 功能
M95080-A125
M95080-A145
Automotive 8-Kbit serial SPI bus EEPROMs
with high-speed clock
Datasheet - production data
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
WFDFPN8 (MF)
2 x 3 mm
Features
Compatible with the Serial Peripheral Interface
(SPI) bus
Memory array
– 8 Kbit (1 Kbyte) of EEPROM
– Page size: 32 byte
– Write protection by block: 1/4, 1/2 or whole
memory
– Additional Write lockable Page
(Identification page)
Extended temperature and voltage ranges
– Up to 125 °C (VCC from 1.7 V to 5.5 V)
– Up to 145 °C (VCC from 2.5 V to 5.5 V)
High speed clock frequency
– 20 MHz for VCC 4.5 V
– 10 MHz for VCC 2.5 V
– 5 MHz for VCC 1.7 V
Schmitt trigger inputs for noise filtering
Short Write cycle time
– Byte Write within 4 ms
– Page Write within 4 ms
Write cycle endurance
– 4 million Write cycles at 25 °C
– 1.2 million Write cycles at 85 °C
– 600 k Write cycles at 125 °C
– 400 k Write cycles at 145 °C
Data retention
– 50 years at 125 °C
– 100 years at 25 °C
ESD Protection (Human Body Model)
– 4000 V
Packages
– RoHS-compliant and halogen-free
(ECOPACK2®)
February 2016
This is information on a product in full production.
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M95080-A145 pdf, 数据表
Signal description
2 Signal description
M95080-A125 M95080-A145
All input signals must be held high or low (according to voltages of VIH or VIL, as specified in
Table 13 and Table 14). These signals are described below.
2.1 Serial Data output (Q)
This output signal is used to transfer data serially out of the device during a Read operation.
Data is shifted out on the falling edge of Serial Clock (C), most significant bit (MSB) first. In
all other cases, the Serial Data output is in high impedance.
2.2 Serial Data input (D)
This input signal is used to transfer data serially into the device. D input receives
instructions, addresses, and the data to be written. Values are latched on the rising edge of
Serial Clock (C), most significant bit (MSB) first.
2.3 Serial Clock (C)
This input signal allows to synchronize the timing of the serial interface. Instructions,
addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial
Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4 Chip Select (S)
Driving Chip Select (S) low selects the device in order to start communication. Driving Chip
Select (S) high deselects the device and Serial Data output (Q) enters the high impedance
state.
2.5 Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
2.6 Write Protect (W)
This pin is used to write-protect the Status Register.
2.7 VSS ground
VSS is the reference for all signals, including the VCC supply voltage.
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M95080-A145 equivalent, schematic
Instructions
M95080-A125 M95080-A145
4.1 Write Enable (WREN)
The WREN instruction must be decoded by the device before a write instruction (WRITE,
WRSR, WRID or LID).
As shown in Figure 5, to send this instruction to the device, Chip Select (S) is driven low, the
bits of the instruction byte are shifted in (MSB first) on Serial Data Input (D) after what the
Chip Select (S) input is driven high and the WEL bit is set (Status Register bit).
Figure 5. Write Enable (WREN) sequence
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4.2 Write Disable (WRDI)
One way of resetting the WEL bit (in the Status Register) is to send a Write Disable
instruction to the device.
As shown in Figure 6, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in (MSB first), on Serial Data Input (D), after
what the Chip Select (S) input is driven high and the WEL bit is reset (Status Register bit).
If a Write cycle is currently in progress, the WRDI instruction is decoded and executed and
the WEL bit is reset to 0 with no effect on the ongoing Write cycle.
Figure 6. Write Disable (WRDI) sequence
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