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PDF ( 数据手册 , 数据表 ) DK2052

零件编号 DK2052
描述 HIGH PERFORMANCE WIDEBAND RF PLL/VCO
制造商 RF Micro Devices
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DK2052 数据手册, 描述, 功能
RF2052
HIGH PERFORMANCE WIDEBAND RF
PLL/VCO WITH INTEGRATED RF MIXER
Package: QFN, 32-Pin, 5mmx5mm
Features
30MHz to 2.5GHz Frequency
Range
Fractional-N Synthesizer
Very Fine Frequency Resolution
1.5Hz for 26MHz Reference
Low Phase Noise VCO
On-Chip Crystal-Sustaining
Circuit With Programmable
Loading Capacitors
High-Linearity RF Mixer
Integrated LO Buffer
Mixer Input IP3 +18dBm
Mixer Bias Adjustable for Low
Power Operation
2.7V to 3.6V Power Supply
Low Current Consumption
55mA to 75mA at 3V
3-Wire Serial Interface
Applications
CATV Head-Ends
Digital TV Up/Down Converters
Digital TV Repeaters
Multi-Dwelling Units
Cellular Repeaters
Frequency Band Shifters
UHF/VHF Radios
Software Defined Radios
Satellite Communications
Super-Heterodyne Radios
BPSK Modulator
VCO
LO
divider
Synth
Frac-N
sequence
generator
Charge
pump
N divider
Phase /
freq
detector
Mixer
Ref
divider
Functional Block Diagram
Product Description
The RF2052 is a low power, high performance, wideband RF frequency conversion
chip with integrated local oscillator (LO) generation and RF mixer. The RF synthe-
sizer includes an integrated fractional-N phase locked loop with voltage controlled
oscillators (VCOs) and dividers to produce a low-phase noise LO signal with a very
fine frequency resolution. The buffered LO output drives the built-in RF mixer which
converts the signal into the required frequency band. The mixer bias current can be
programmed dependent on the required performance and available supply current.
The LO generation blocks have been designed to continuously cover the frequency
range from 300MHz to 2400MHz. The RF mixer is very broad band and operates
from 30MHz to 2500MHz at the input and output, enabling both up and down con-
version. An external crystal of between 10MHz and 52MHz or an external reference
source of between 10MHz and 104MHz can be used with the RF2052 to accom-
modate a variety of reference frequency options.
All on-chip registers are controlled through a simple three-wire serial interface. The
RF2052 is designed for 2.7V to 3.6V operation for compatibility with portable, bat-
tery powered devices. It is available in a plastic 32-pin, 5mmx5mm QFN package.
Optimum Technology Matching® Applied
GaAs HBT
GaAs MESFET
InGaP HBT
SiGe BiCMOS
Si BiCMOS
SiGe HBT
GaAs pHEMT
Si CMOS
Si BJT
GaN HEMT
RF MEMS
LDMOS
DS140110
RF MICRO DEVICES®, RFMD®, Optimum Technology Matching®, Enabling Wireless Connectivity™, PowerStar®, POLARIS™ TOTAL RADIO™ and UltimateBlue™ are trademarks of RFMD, LLC. BLUETOOTH is a trade-
mark owned by Bluetooth SIG, Inc., U.S.A. and licensed for use by RFMD. All other trade names, trademarks and registered trademarks are the property of their respective owners. ©2006, RF Micro Devices, Inc.
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
1 of 37







DK2052 pdf, 数据表
RF2052
Typical Performance Characteristics: RF Mixer - VDD=3V, TA=25°C unless stated, as measured on RF2052 evaluation board,
for application schematic see page 34.
Mixer Conversion Gain, IF Output=100MHz
0
-1
-2
-3
-4
-5
-6
-7
-8 -40°C
-9
+27°C
+85°C
-10
250
500
750
1000
1250
1500
1750
RF Input Frequency (MHz)
Gain versus Temperature and Supply Voltage
(excluding losses in PCB and Baluns)
0.0
2.7V
-0.5 3.0V
3.6V
-1.0
-1.5
-2.0
-2.5
-3.0
-40
-20
0 20 40 60
Temperature (°C)
80 100
Operating Current versus Temperature and
Supply Voltage
80
75
70
65
60
55
50
001
-40°C, +2.7V
-40°C, +3.0V
-40°C, +3.6V
+27°C, +2.7V
+27°C, +3.0V
+27°C, +3.6V
+85°C, +2.7V
+85°C, +3.0V
+85°C, +3.6V
010 011 100 101
Mixer Bias Current Setting (MIX2_IDD)
Mixer Typical RF and LO Leakage at IF Output
0
-10
-20
-30
-40
-50
-60
IF Output at 100MHz
RF Leakage
LO Leakage (High Side)
-70
250
500
750
1000
1250
1500
1750
RF Input Frequency (MHz)
Mixer Typical IF and LO Leakage at RF Input
0
100MHz IF Leakage to RF Port
-10 LO Leakage (High Side) to RF
-20
-30
-40
-50
-60
-70
-80
250
500
750
1000
1250
1500
1750
RF Input Frequency (MHz)
0
-10
-20
-30
-40
-50
-60
-70
0
Mixer Typical LO Leakage at IF Output
IF Output=100MHz
-40 Deg C
+27 Deg C
+85 Deg C
500
1000
1500
2000
RF Input Frequency (MHz)
2500
8 of 37
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
DS140110







DK2052 equivalent, schematic
RF2052
lowed by a ‘1’ (to indicate a read operation), followed by a seven bit address. A 1.5 bit delay is introduced before the sixteen bit
data word representing the register content is presented to the receiver.
Note that since the serial bus does not require the presence of the crystal clock, it is necessary to insert an additional rising
clock edge before the ENX line is set low to ensure the address is read correctly.
Hardware Control
Three hardware control pins are provided: ENBL, MODE, and RESETB.
ENBL Pin
The ENBL pin has two functions: to enable the analog circuits in the chip and to trigger the VCO band selection as described in
the VCO section on page 10.
ENBL Pin
Low
Low
High
High
REFSTBY Bit
0
1
0
1
XO and Bias Block
Off
On
On
On
Analogue Block
Off
Off
On
On
Digital Block
On
On
On
On
As outlined in the VCO section the chip has a built-in automatic VCO band selection to tune the selected VCO to the desired fre-
quency. The band selection is initiated when the ENBL pin is taken high. Every time the frequency of the synthesizer is re-pro-
grammed, the ENBL has to be inserted high to initiate the automatic VCO band selection (VCO coarse tune).
RESETB Pin
The RESETB pin is a hardware reset control that will reset all digital circuits to their start-up state when asserted low. The
device includes a power-on-reset function, so this pin should not normally be required, in which case it should be connected to
the positive supply.
MODE Pin
The MODE pin controls which PLL programming register bank is active.
For normal operation of the RF2052 the MODE pin should be set high to select the default PLL2 programming registers. It is
possible to set the FULLD bit in the CFG1 register high. This allows the MODE pin to select either PLL1 register bank
(MODE=low) or PLL2 register bank (MODE=high). This may be useful for some applications where two LO frequencies can be
programmed into the registers then the MODE pin used to toggle between them. The ENBL pin will also need to be cycled to re-
lock the synthesizer for each frequency.
ENBL
MODE
t1
t2
Parameter
t1
t2
Description
MODE setup time
MODE hold time
Time
>5 ns
>5 ns
16 of 37
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
DS140110










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