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PDF ( 数据手册 , 数据表 ) M93C46-DRE

零件编号 M93C46-DRE
描述 MICROWIRE serial EEPROM
制造商 STMicroelectronics
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M93C46-DRE 数据手册, 描述, 功能
M93Cx6-DRE
16-Kbit, 8-Kbit, 4-Kbit, 2-Kbit and 1-Kbit (8-bit or 16-bit wide)
MICROWIRE™ serial EEPROM 105 °C Operation
Datasheet - production data
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
WFDFPN8 (MF)
2 x 3 mm
Features
Industry standard MICROWIRE™ bus
Memory array: 1 Kb, 2 Kb, 4 Kb, 8 Kb or 16 Kb
Dual organization: by word (x16) or byte (x8)
Write
– Byte within 4 ms
– Word within 4 ms
READY/BUSY signal during programming
2 MHz clock rate
Sequential read operation
Single supply voltage: 1.8 V to 5.5 V
Extended temperature range: -40 °C up to 105
°C
Enhanced ESD protection
Write cycle endurance
– 4 million Write cycles at 25 °C
– 1.2 million Write cycles at 85 °C
– 900 k Write cycle at 105°C
Data retention
– more than 50 years at 105 °C
– 200 years at 55 °C
Packages
– RoHS-compliant and Halogen-free
(ECOPACK2®)
Table 1. Device summary
Reference
Part number
M93Cx6-DRE
M93C46-DRE
M93C56-DRE
M93C66-DRE
M93C76-DRE
M93C86-DRE
November 2015
This is information on a product in full production.
DocID028496 Rev 1
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www.st.com







M93C46-DRE pdf, 数据表
Connecting to the serial bus
2 Connecting to the serial bus
M93Cx6-DRE
Figure 3 shows an example of three memory devices connected to an MCU, on a serial bus.
Only one device is selected at a time, so only one device drives the Serial Data output (Q)
line at a time, the other devices are high impedance.
The pull-down resistor R (represented in Figure 3) ensures that no device is selected if the
bus master leaves the S line in the high impedance state.
In applications where the bus master may be in a state where all inputs/outputs are high
impedance at the same time (for example, if the bus master is reset during the transmission
of an instruction), the clock line (C) must be connected to an external pull-down resistor so
that, if all inputs/outputs become high impedance, the C line is pulled low (while the S line is
pulled low): this ensures that C does not become high at the same time as S goes low, and
so, that the tSLCH requirement is met. The typical value of R is 100 kΩ.
Figure 3. Bus master and memory devices on the serial bus
633
6##
2
3$/
3$)
3#+
"USMASTER
#1$
6##
633
#1$
6##
633
# 1 $ 6##
633
#3 #3 #3
2
-XXX
MEMORYDEVICE
2
-XXX
MEMORYDEVICE
2
-XXX
MEMORYDEVICE
3 /2'
3 /2'
3 /2'
!)B
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M93C46-DRE equivalent, schematic
Instructions
M93Cx6-DRE
5.2.5
Erase Byte or Word
The Erase Byte or Word (ERASE) instruction sets the bits of the addressed memory byte (or
word) to 1. Once the address has been correctly decoded, the falling edge of the Chip
Select Input (S) starts the self-timed Erase cycle. The completion of the cycle can be
detected by monitoring the READY/BUSY line, as described in Section 6: READY/BUSY
status.
Figure 7. ERASE, ERAL sequences
%2!3%
3
$
   !N !
#(%#+
34!453
1
%2!3%
!,,
3
$
!$$2
/0
#/$%
"539
2%!$9
     8N 8
#(%#+
34!453
5.2.6
1
!$$2
/0
#/$%
"539
2%!$9
1. For the meanings of An and Xn, please see Table 5, Table 6 and Table 7.
!)"
Erase All
The Erase All Memory (ERAL) instruction erases the whole memory (all memory bits are set
to 1). The format of the instruction requires that a dummy address be provided. The Erase
cycle is conducted in the same way as the Erase instruction (ERASE). The completion of
the cycle can be detected by monitoring the READY/BUSY line, as described in Section 6:
READY/BUSY status.
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DocID028496 Rev 1










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