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零件编号 | M93S66-W | ||
描述 | MICROWIRE bus EEPROM | ||
制造商 | STMicroelectronics | ||
LOGO | |||
1 Page
M93S46-W M93S56-W
M93S66W
4 Kbit, 2 Kbit and 1 Kbit serial MICROWIRE bus EEPROM with
write protection
Datasheet - production data
PDIP8 (BN)
TSSOP8 (DW)
169 mil width
SO8 (MN)
150 mil width
MSv35377V1
Features
• Compatible with MICROWIRE bus serial
interface
• Memory array
− 1 Kbit, 2 Kbit or 4 Kbit of EEPROM
− Organized by word (16b)
− Page = 4 words
• Write
− Byte write within 5 ms
− Page write within 5 ms
− Ready/busy signal during programming
• User defined write protected area
• High-speed clock: 2 MHz
• Single supply voltage:
− 2.5 V to 5.5 V
• Operating temperature range:
• -40 °C up to +85 °C.
• Enhanced ESD protection
• More than 4 million write cycles
• More than 200-year data retention
Packages
• PDIP8 ECOPACK®1
• TSSOP8 ECOPACK®2
• SO8 ECOPACK®2
January 2015
DocID5124 Rev 7
This is information on a product in full production
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www.st.com
Operating features
M93S46-W M93S56-W M93S66W
3 Operating features
The device is compatible with the MICROWIRE protocol. All instructions, addresses and
input data bytes are shifted into the device, most significant bit first. The Serial Data Input
(D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes
high. All output data bytes are shifted out of the device, most significant bit first. The Serial
Data Output (Q) is latched on the rising edge of the Serial Clock (C) after the read
instruction has been clocked into the device.
The M93Sx6 is accessed by a set of instructions which includes Read, Write, Page Write,
Write All and instructions used to set the memory protection. These are summarized in
Table 2: "Instruction set for the M93S46" and Table 3: "Instruction set for the M93S66,
M93S56").
A Read Data from Memory (READ) instruction loads the address of the first word to be
read into an internal address counter. The data contained at this address is then clocked
out serially. The address counter is automatically incremented after the data is output and,
if the Chip Select Input (S) is held High, the M93Sx6 can output a sequential stream of data
words. In this way, the memory can be read as a data stream, or continuously as the
address counter automatically rolls over to 00h when the highest address is reached.
Writing data is internally self-timed (the external clock signal on Serial Clock (C) may be
stopped or left running after the start of a Write cycle) and does not require an erase cycle
prior to the Write instruction. The Write instruction writes 16 bits at a time into one of the
word locations of the M93Sx6, the Page Write instruction writes up to 4 words of 16 bits to
sequential locations, assuming in both cases that all addresses are outside the Write
Protected area.
Up to 4 words may be written with help of the Page Write instruction and the whole memory
may also be erased, or written to a predetermined pattern by using the Write All instruction,
within the time required by a write cycle (tW).
After the start of the write cycle, a Busy/Ready signal is available on Serial Data Output (Q)
when Chip Select Input (S) is driven High.
Within the memory, a user defined area may be protected against further Write instructions.
The size of this area is defined by the content of a Protection Register, located outside of
the memory array.
As a final protection step, data in this user defined area may be permanently protected by
programming a One Time Programming bit (OTP bit) which locks the Protection Register
content.
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Instructions
M93S46-W M93S56-W M93S66W
After the last data bit has been sampled, the Chip Select Input (S) must be taken Low
before the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought Low
before or after this specific time frame, the self-timed programming cycle will not be started,
and the addressed location will not be programmed.
While the M93Sx6 is performing a write cycle, and after a delay (tSLSH) before the status
information becomes available, Chip Select Input (S) can be driven High to monitor the
status of the write cycle. Serial Data Output (Q) is driven Low while the M93Sx6 is still
busy, and High when the cycle is complete, and the M93Sx6 is ready to receive a new
instruction. The M93Sx6 ignores any data on the bus while it is busy on a write cycle. Once
the M93Sx6 is Ready, Serial Data Output (Q) is driven High, and remains in this state until
a new start bit is decoded or the Chip Select Input (S) is brought Low.
Programming is internally self-timed, so the external Serial Clock (C) may be disconnected
or left running after the start of a write cycle.
5.6 Write protection and protect register
The Protection Register on the M93Sx6 is used to adjust the amount of memory that is to
be write protected. The write protected area extends from the address given in the
Protection Register, up to the top address in the M93Sx6 device.
Two flag bits are used to indicate the Protection Register status:
• Protection Flag: this is used to enable/disable protection of the write-protected area of
the M93Sx6 memory
• OTP bit: when set, this disables access to the Protection Register, and thus prevents
any further modifications to the value in the Protection Register.
The lower-bound memory address is written to the Protection Register using the Protection
Register Write (PRWRITE) instruction. It can be read using the Protection Register Read
(PRREAD) instruction.
The Protection Register Enable (PREN) instruction must be executed before any
PRCLEAR, PRWRITE or PRDS instruction, and with appropriate levels applied to the
Protection Enable (PRE) and Write Enable (W) signals.
Write-access to the Protection Register is achieved by executing the following sequence:
• Execute the Write Enable (WEN) instruction
• Execute the Protection Register Enable (PREN) instruction
• Execute one PRWRITE, PRCLEAR or PRDS instructions, to set a new boundary
address in the Protection Register, to clear the protection address (to all 1s), or
permanently to freeze the value held in the Protection Register.
Protection register read
The Protection Register Read (PRREAD) instruction outputs, on Serial Data Output (Q),
the content of the Protection Register, followed by the Protection Flag bit. The Protection
Enable (PRE) signal must be driven High before and during the instruction.
As with the Read Data from Memory (READ) instruction, a dummy 0 bit is output first.
Since it is not possible to distinguish between the Protection Register being cleared (all 1s)
or having been written with all 1s, the user must check the Protection Flag status (and not
the Protection Register content) to ascertain the setting of the memory protection.
Protection register enable
The Protection Register Enable (PREN) instruction is used to authorize the use of
instructions that modify the Protection Register (PRWRITE, PRCLEAR, PRDS). The
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DocID5124 Rev 7
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页数 | 30 页 | ||
下载 | [ M93S66-W.PDF 数据手册 ] |
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