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PDF ( 数据手册 , 数据表 ) ZL30250

零件编号 ZL30250
描述 3-Output Any-to-Any Clock Multiplier and Frequency Synthesizer ICs
制造商 Microsemi
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ZL30250 数据手册, 描述, 功能
Register Map: Section 6.2
Features
Four Input Clocks
One crystal/CMOS input
Two differential/CMOS inputs
One single-ended/CMOS input
Any input frequency from 9.72MHz to 1250MHz
(9.72MHz to 300MHz for CMOS)
Clock selection by pin or register control
Low-Jitter Fractional-N APLL and 3 Outputs
Any output frequency from <1Hz to 1035MHz
High-resolution fractional frequency conversion
with 0ppm error
Easy-to-configure, encapsulated design
requires no external VCXO or loop filter
components
Each output has independent dividers
Output jitter as low as 0.16ps RMS (12kHz-
20MHz integration band)
Outputs are CML or 2xCMOS, can interface to
LVDS, LVPECL, HSTL, SSTL and HCSL
In 2xCMOS mode, the P and N pins can be
different frequencies (e.g. 125MHz and 25MHz)
Per-output supply pin with CMOS output
voltages from 1.5V to 3.3V
ZL30250, ZL30251
4-Input, 3-Output Any-to-Any Clock
Multiplier and Frequency Synthesizer ICs
Data Sheet
March 2015
Ordering Information
ZL30250LDG1
ZL30250LDF1
ZL30251LDG1
ZL30251LDF1
32 Pin QFN
32 Pin QFN
32 Pin QFN
32 Pin QFN
Trays
Tape and Reel
Trays
Tape and Reel
Matte Tin
Package size: 5 x 5 mm
-40C to +85C
Precise output alignment circuitry and per-
output phase adjustment
Per-output enable/disable and glitchless
start/stop (stop high or low)
General Features
Automatic self-configuration at power-up from
external (ZL30250) or internal (ZL30251)
EEPROM; up to four configs, pin-selectable
SPI or I2C processor Interface
Numerically controlled oscillator mode
Spread-spectrum modulation mode
Tiny 5x5mm QFN package
Easy-to-use evaluation software
Applications
Frequency conversion and frequency synthesis in
a wide variety of equipment types
IC1P, IC1N
HSDIV1
APLL
HSDIV1
DIV1
IC2P, IC2N
HSDIV2
~3.7 to 4.2GHz,
IC3P/GPIO3
XA
xtal
HSDIV3
NCO
SS
Fractional-N
Figure 6
HSDIV2
DIV2
DIV3
XB driver ×2
Microprocessor Port
(SPI or I2C Serial)
and HW Control and Status Pins
OC1P, OC1N
VDDO1
OC2P, OC2N
VDDO2
OC3P, OC3N
VDDO3
Figure 1 - Functional Block Diagram
1
Microsemi Confidential
Copyright 2015. Microsemi Corporation. All Rights Reserved.







ZL30250 pdf, 数据表
ZL30250, ZL30251
Data Sheet
Table 1 - Pin Descriptions (continued)
Pin #
Name
Type
Description
Auto-Configure [1:0] / General Purpose I/O 0 and 1
28
27
AC0/GPIO0
AC1/GPIO1
Auto Configure: On the rising edge of RSTN these pins behave as AC[1:0] and
I/O specify one of the configurations stored in EEPROM. See section 5.2.
General-Purpose I/O: After reset these pins are GPIO0 and GPIO1. GPIOCR1
configures the pins. Their states are indicated in GPIOSR.
Factory Test / General Purpose I/O 2
Factory Test: On the rising edge of RSTN the pin behaves as TEST. Factory
26
TEST/GPIO2
I/O
test mode is enabled when TEST is high. For normal operation TEST must be
low on the rising edge of RSTN.
General-Purpose I/O: After reset this pin is GPIO2. GPIOCR2 configures the
pin. It state is indicated in GPIOSR.
Interface Mode 0 / SPI Chip Select (Active Low)
Interface Mode: On the rising edge of RSTN the pin behaves as IF0 and,
together with IF1, specifies the interface mode for the device. See section 5.2.
32
IF0/CSN
I/O SPI Chip Select: After reset this pin is CSN. When the device is configured as
a SPI slave, an external SPI master must assert (low) CSN to access device
registers. When the device is configured as a SPI master (ZL30250 only), the
device asserts CSN to access an external SPI EEPROM during auto-
configuration.
I2C Clock / SPI Clock
I2C Clock: When the device is configured as an I2C slave, an external I2C
master must provide the I2C clock signal on the SCL pin.
31
SCL/SCLK
I/O SPI Clock: When the device is configured as a SPI slave, an external SPI
master must provide the SPI clock signal on SCLK. When the device is
configured as a SPI master(ZL30250 only), the device drives SCLK as an
output to clock accesses to an external SPI EEPROM during auto-
configuration.
Interface Mode 1 / SPI Master-In-Slave-Out
Interface Mode: On the rising edge of RSTN the pin behaves as IF1 and,
together with IF0, specifies the interface mode for the device. See section 5.2.
SPI MISO: After reset this pin is MISO. When the device is configured as a SPI
slave, the device outputs data to an external SPI master on MISO during SPI
1
IF1/MISO
I/O read transactions. When the device is configured as a SPI master (ZL30250
only), the device receives data on MISO from an external SPI EEPROM during
auto-configuration.
Note: On rev A parts, in I2C interface mode this pin toggles between driving low and high-
impedance during register accesses. Therefore in I2C mode this pin must not be wired directly to
VDD. To implement a static high value on IF1/MISO, wire it to VDD through a resistor
(approximately 10krecommended).
I2C Data / SPI Master-Out-Slave-In
2
SDA/MOSI
I/O
I2C Data: When the device is configured as an I2C slave, SDA is the
bidirectional data line between the device and an external I2C master.
SPI MOSI: When the device is configured as a SPI slave, an external SPI
8
Microsemi Confidential







ZL30250 equivalent, schematic
ZL30250, ZL30251
Data Sheet
5.7.1 Output Enable, Signal Format, Voltage and Interfacing
To use an output, the output driver must be enabled by setting OCxCR2.OCSF0, and the per-output dividers must
be enabled by setting the appropriate bit in the OCEN register. The per-output dividers include the medium-speed
divider, the low-speed divider and the associated phase adjustment/alignment circuitry and start/stop logic.
Using the OCxCR2.OCSF register field, each output pair can be disabled or configured as a CML output, an HSTL
output, or one or two CMOS outputs. When an output is disabled it is high impedance, and the output driver is in a
low-power state. In CMOS mode, the OCxN pin can be disabled, in phase or inverted vs. the OCxP pin. In CML
mode the normal 800mV VOD differential voltage is available as well as a half-swing 400mV VOD. All of these
options are specified by OCxCR2.OCSF. The clock to the output driver can inverted by setting OCxCR2.POL=1.
The CMOS/HSTL output driver can be set to any of four drive strengths using OCxCR2.DRIVE.
Each output has its own power supply pin to allow CMOS or HSTL signal swing from 1.5V to 3.3V for glueless
interfacing to neighboring components. If OCSF is set to HSTL mode then a 1.5V power supply voltage should be
used to get a standards-compliant HSTL output. Note that differential (CML) outputs must have a power supply of
3.3V.
The differential outputs can be easily interfaced to LVDS, LVPECL, CML, HCSL, HSTL and other differential inputs
on neighboring ICs using a few external passive components. See Figure 18 for examples.
5.7.2 Output Frequency Configuration
The frequency of each output is determined by the configuration of the APLL, the high-speed dividers and the per-
output dividers. Each output can be connected to either high-speed divider 1 (HSDIV1) or 2 (HSDIV2) using the
OCxCR3.DIVSEL field.
Each output has two output dividers, a 7-bit medium-speed divider (OCxCR1.MSDIV) and a 24-bit low-speed
output divider (LSDIV field in the OCxDIV registers). These dividers are in series, medium-speed divider first then
output divider. These dividers produce signals with 50% duty cycle for all divider values including odd numbers.
The low-speed divider can only be used if the medium-speed divider is used (i.e. OCxCR1.MSDIV>0).
Since each output has its own independent dividers, the device can output families of related frequencies that have
an APLL HSDIV output frequency as a common multiple. For example, for Ethernet clocks, a 625MHz HSDIV
output clock can be divided by four for one output to get 156.25MHz, divided by five for another output to get
125MHz, and divided by 25 for another output to get 25MHz. Similarly, for SDH/SONET clocks, a 622.08MHz
HSDIV output clock can be divided by 4 to get 155.52MHz, by 8 to get 77.76MHz, by 16 to get 38.88MHz or by 32
to get 19.44MHz.
Two Different Frequencies in 2xCMOS Mode
When an output is in 2xCMOS mode it can be configured to have the frequency of the OCxN clock be an integer
divisor of the frequency of the OCxP clock. Examples of where this can be useful:
125MHz on OCxP and 25MHz on OCxN for Ethernet applications
77.76MHz on OCxP and 19.44MHz on OCxN for SONET/SDH applications
25MHz on OCxP and 1Hz (i.e. 1PPS) on OCxN for telecom applications with Synchronous Ethernet and
IEEE1588 timing
An output can be configured to operate like this by setting the LSDIV value in the OCxDIV registers to OCxP_freq /
OCxN_freq - 1 and setting OCxCR3.LSSEL=0 and OCxCR3.NEGLSD=1. Here are some notest about this dual-
frequency configuration option:
16
Microsemi Confidential










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