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PDF ( 数据手册 , 数据表 ) 8T49N028

零件编号 8T49N028
描述 Multiple Frequency Clock Generator
制造商 Integrated Device Technology
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8T49N028 数据手册, 描述, 功能
FemtoClock® NG Crystal-to-3.3V, 2.5V
Multiple Frequency Clock Generator
w/Fanout Buffer
8T49N028
DATA SHEET
General Description
The 8T49N028 is a low RMS phase jitter Clock Synthesizer with
selectable internal crystal oscillator or external clock references and
eight outputs, configurable as either LVDS, LVPECL or High
Impedance.
After power up, two frequency select pins determine one of up to four
different sets of factory preprogrammed crystal or input frequency
and output frequency configurations. From a single input reference,
as many as three different output frequencies may be selected for
the output banks: two of these frequencies can be generated by the
internal crystal oscillator, and/or external clock pre-divider, and/or A
output divider, and/or B output divider. The third output frequency is
from the B output divider. Device pre-programming can be
overwritten through the provided I2C interface.
Examples of valid frequency configuration setups illustrate this
device's flexibility, and are shown in Table 3A. The specific internal
register settings for each of the four frequency sets are specified by
an IDT order code. Custom codes can be provided by contacting
IDT.
Features
Fourth Generation FemtoClock NG PLL technology
Eight selectable LVPECL or LVDS outputs (bank selectable, two
output channels per bank)
CLK, nCLK input pair can accept the following differential input
levels: LVPECL, LVDS, HCSL
FemtoClock NG VCO Range: 1.92GHz - 2.5GHz
Bank A and B output frequencies are mux selectable from internal
crystal oscillator, reference clock input, output divider A or output
divider B
Clock from OUTPUT DIVIDER A, RMS phase jitter at 156.25MHz
(12KHz - 20MHz): 225fs (typical)
Clock from OUTPUT DIVIDER B, RMS phase jitter at 156.25MHz
(12KHz - 20MHz): 219fs (typical)
Clock from OUTPUT DIVIDER B, RMS phase jitter at 156.25MHz
(10kHz - 1MHz): 165fs (typical) Full 2.5V or 3.3V power supply
Full 2.5V or 3.3V power supply
I2C programming interface
PCI Express (2.5 Gb/S), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) jitter
compliant
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
Pin Assignment
Q0
nQ0
Q1
nQ1
VCCO_A
nc
nc
VCCO_B
Q2
nQ2
Q3
nQ3
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 32
6 31
7 8T49N028 30
8 29
9 28
10 27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
VEE
Q4
nQ4
Q5
nQ5
VCCO_C
VCCO_D
Q6
nQ6
Q7
nQ7
VEE
8T49N028 REVISION 1 10/16/14
48-pin, 7mm x 7mm VFQFN Package
1 ©2014 Integrated Device Technology, Inc.







8T49N028 pdf, 数据表
8T49N028 DATA SHEET
Table 3H. PLL Output Divider PNA and NA Coding
Register Bit
Register Bit
PNAn[1:0]
00
NAn[5:0]
000000
00 000001
00 000010
00 …
00 111111
01 000000
01 000001
01 000010
01 …
01 111111
10 000000
10 000001
10 000010
10 …
10 111111
11 000000
11 000001
11 000010
11 …
11 111111
Output Divider
n/a
n/a
4
NAn * 2
126
n/a
n/a
6
NAn * 3
189
n/a
n/a
10
NAn * 5
315
n/a
n/a
4
NAn * 2
126
Output Frequency Range
fOUT_MIN (MHz)
n/a
fOUT_MAX (MHz)
n/a
n/a n/a
480.00
625.00
(960 ÷ NAn)
(1250 ÷ NAn)
15.24 (approx.)
19.84 (approx.)
n/a n/a
n/a n/a
320.00
416.67
(640 ÷ NAn)
(833.33 ÷ NAn)
10.16 (approx.)
13.23 (approx.)
n/a n/a
n/a n/a
192.00
250.00
(384 ÷ NAn)
(500 ÷ NAn)
6.10 (approx.)
7.94 (approx.)
n/a n/a
n/a n/a
480.00
625.00
(960 ÷ NAn)
(1250 ÷ NAn)
15.24 (approx.)
19.84 (approx.)
Table 3I. PLL Output Divider NB Coding
Register Bit
NBn[6:0]
000000X
Output Divider N
n/a
0000010
0000011
2
3
0000100
4
0000101
000011X
5
6
000100X
8
000101X
000110X
10
12
000111X
14
001000X
16
NB (even integer)
111101X
124
111111X
126
NOTE: X denotes “don’t care”.
REVISION 1 10/16/14
8
Output Frequency Range
fOUT_MIN (MHz)
fOUT_MAX (MHz)
n/a
960.00
1250.00
640.00
833.33
480.00
625.00
384.00
500.00
320.00
416.67
240.00
312.5
192.00
250.00
160.00
208.33
137.14 (approx.)
178.57 (approx.)
120.00
156.25
(1920 ÷ NBn)
(2500 ÷ NBn)
15.48 (approx.)
20.16 (approx.)
15.24 (approx.)
19.84 (approx.)
FEMTOCLOCK® NG CRYSTAL-TO-3.3V, 2.5V MULTIPLE FREQUENCY
CLOCK GENERATOR W/FANOUT BUFFER







8T49N028 equivalent, schematic
8T49N028 DATA SHEET
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
tR / tF
Output
Rise/Fall Time
LVPECL
Outputs
LVDS
Outputs
20% - 80%, LVDS_SEL = 0
20% - 80%, LVDS_SEL = 1
250 600 ps
270 500 ps
odc Output Duty Cycle
Output Divider N 3;
LVDS_SEL = 0 or 1
Output Divider N = 3;
LVDS_SEL = 0 or 1
47
45
53 %
55 %
tLOCK
PLL Lock Time; LOCK
NOTE 4, 5
Output
20 ms
tTRANSITION
Transition
Time;
NOTE 4, 5
LOCK
Output
20 ms
NOTE: VCCO_X denotes VCCO_A + VCCO_B + VCCO_C + VCCO_D.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: The input frequency of the differential input is a physical limitation of the device. Follow the PLL setting to insure proper functionality
of the device.
NOTE 2: Refer to Phase Noise Plots.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: Refer to tLOCK and tTRANSITION in Parameter Measurement Information.
REVISION 1 10/16/14
16 FEMTOCLOCK® NG CRYSTAL-TO-3.3V, 2.5V MULTIPLE FREQUENCY
CLOCK GENERATOR W/FANOUT BUFFER










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8T49N028Multiple Frequency Clock GeneratorIntegrated Device Technology
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