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PDF ( 数据手册 , 数据表 ) CE2826

零件编号 CE2826
描述 6-Channel Audio Codec
制造商 CEI Microelectronics
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CE2826 数据手册, 描述, 功能
Microelectronics
CE2826
6-Channel Audio Codec, 24-bit, 192kHz
DESCRIPTION
The CE2826 is a mixed signal CMOS monolithic audio
Codec. It contains six multi-bit sigma delta DAC and a
stereo ADC, Ideal for DVD and audio processing
application.
The DAC consists of 128-time interpolation filters, 3rd
order multi-bit Σ∆ modulators, switch capacitors and
analog reconstruction filters. The Σ∆ converter offers
superior differential linearity, with minimum distortion due
to component mis-match. high tolerance to clock jitter.
Additionally it includes separated digital volume control
for each channel.
FEATURES
• Six Channel Audio DAC.
- 104 dB SNR (A Weighted).
- -91 dB THD + N Ratio (A Weighted).
- 32K - 192 KHz. Sampling Rates.
- On -chip Reconstruction Filters.
- Independent Digital Volume Control.
• Stereo Audio ADC.
- Up to 96K sampling Rate.
• I2S, Left and Right Justified Digital I/F Formats.
• 2-wire Serial Control Interface.
• 3.3 Volt Power Supply.
The ADC utilizes cascaded Σ∆ architecture. The internal
digital filter has a 20K bandwidth. It support sampling
frequency up to 96K Hz.
Applications
• Digital Surround Sound For Home Theatre
• DVD
• Car Audio.
XCK
LRCK
BCK
77
78
DIN1
DIN2
DIN3
80
80
77
DOUT
77
Clock Rate
Detect'n
DIGITAL
AUDIO
I/F
SDA SCL
Control Interface
CE2826
Σ∆
Mod.
D/A
D/A
INTERPOLATION
FILTER
Σ∆
Mod.
D/A
D/A
Σ∆
Mod.
D/A
D/A
HIGH PASS
FILTER
DECIMATION
FILTER
A/D
AR1
AL1
AR2
AL2
AR3
AL3
AINR
AINL
CEI Microelectronics Co. Ltd.
1-20
February 3, 2005







CE2826 pdf, 数据表
CE2826
INFINITE ZERO DETECTION
The CE2826 has an Infinite Zero Detection circuit which detects zero in the Audio Serial Port that lasts for approximately 0.1
sec. By default, the zero detection circuit is on.
Serial Command Port
The user can select the chip operation mode by programming the internal control registers through serial I2C port. The Chip
Address for the CE2826 is 35H. The protocol for write operation consists of sending 3 byte data to CE2826, following each
byte is the acknowledges generated by CE2826. The first byte is the 7-bit Chip Address followed by the read/write bit (read is
high, write is low). The second byte is the control register address. The third byte is the control register data.
Upon power up, all programmable registers are set to default values. Figure 2 describes the serial command port timing
relationship.
Figure 2. Serial Command Port Timing
I2C Bus Control Register Write Example:
first byte
Start
SDA
CA6
11
SCL
1
CA0 R/W ACK A7
1
second byte
A0 ACK D7
third byte
D0 ACK Stop
Example
Set channel 1L volume to 30H:
first byte: [CA R/W] = 6AH
( Note: Chip adrress: CA<6:0> = 35H, R/W =0.)
second byte: register address: A<7:0> = 02H
third byte: data D<7:0> = 30H
8-20 February 3, 2005







CE2826 equivalent, schematic
TIMING DIAGRAM
Figure 3. Audio Serial Interface Timing Requirement
BCK
DIN[1-3]
tbck H
tbck
tbck L
tkd su
LRCK
tkr su
tkr hd
CE2826
tkd hd
Figure 4. Serial Command Port Write Timing Requirement
SDA, SCL
tF
tSCL
tLOW
tHIGH
tR
SDA
tBF tHD,sta
tHD,dat tSU,dat
tSU,sta
tSU,stp
SCL
stop start
start
stop
16-20
February 3, 2005










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