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PDF ( 数据手册 , 数据表 ) 8T49NS010

零件编号 8T49NS010
描述 Clock Synthesizer and Fanout Buffer/Divider
制造商 Integrated Device Technology
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8T49NS010 数据手册, 描述, 功能
Clock Synthesizer
and Fanout Buffer/Divider
8T49NS010
DATA SHEET
General Description
The 8T49NS010 is a Clock Synthesizer and Fanout Buffer/Divider.
When used with an external crystal, the 8T49NS010 generates high
performance timing geared towards the communications and data-
com markets, especially for applications demanding extremely low
phase noise jitter, such as 10, 40 and 100GE.
The 8T49NS010 provides versatile frequency configurations and
output formats and is optimized to deliver excellent phase noise
performance. The device delivers an optimum combination of high
clock frequency and low phase noise performance, combined with
high power supply noise rejection.
The 8T49NS010 supports two types of output levels. FORMAT #1
Outputs provide an output level with 750mV typical swing, and
requires external DC termination. FORMAT #2 Outputs provide a
similar swing level which does not require DC termination.
The device can be configured through an I2C serial interface and is
offered in a lead-free (RoHS6) 56-pin VFQFN package.
The extended temperature range supports telecommunication and
networking end equipment requirements.
Features
Ten differential outputs
The input operates in full differential mode (LVDS, LVPECL) or
single-ended LVCMOS mode
Can be driven from a crystal or differential clock
Support of output power-down
Excellent clock output phase noise
Offset Output Frequency Single-side Band Phase Noise
100kHz
156.25MHz
-144 dBc/Hz
Phase Noise RMS, 12kHz to 20MHz integration range:
84fs (typical)
LVCMOS compatible I2C serial interface
I2C control inputs are 3.3V tolerant
Full 3.3V supply voltage
Lead-free (RoHS 6) 56-pin VFQFN packaging
-40°C to 85°C ambient operating temperature
Additional Ordering Information
Part/Order Number
Package
8T49NS010-156NLGI
56-pin VFQFN
Output Frequency (MHz)
156.25, 312.5, 625, 1250
8T49NS010 REVISION 1 11/19/14
1 ©2014 Integrated Device Technology, Inc.







8T49NS010 pdf, 数据表
8T49NS010 DATA SHEET
PLL Control Register
The PLL control register contains the settings for the PLL reference divider and feedback dividers.
Table 5B. PLL Pre-Divider Register Bit Allocations
Register Bit
Register
D7
D6
D5
D4
D3
D2
20
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
D1
PDIV[1]
D0
PDIV[0]
Table 5C. PLL Pre-Divider Register Function Description
Bits Name
Factory Default
PDIV[1:0]
Pre-Divider (P)
00
Function
00 = x 2 (Default)
01 = ÷1
10 = ÷2
11 = ÷4
Table 5D. PLL FB Divider Register Bit Allocations
Register
0
D7
MDIV[7]
D6
MDIV[6]
D5
MDIV[5]
Register Bit
D4 D3
MDIV[4]
MDIV[3]
D2
MDIV[2]
D1
MDIV[1]
D0
MDIV[0]
Table 5E. PLL FB Divider Register Function Description
Bits Name
Factory Default
MDIV[7:0] FB Divide (M)
0011 0010
Function
0000 0000 = Reserved
0000 0001 = Reserved
0000 0010 = Reserved
0000 0011 = Reserved
0000 1000 = ÷8
0011 0010 = ÷50 (Default)
1111 1111 = ÷255
CLOCK SYNTHESIZER AND FANOUT BUFFER/DIVIDER
8
REVISION 1 11/19/14







8T49NS010 equivalent, schematic
8T49NS010 DATA SHEET
Table 7B. QCLK[0:9] Phase Noise and Jitter Characteristics, VDD_x = 3.3V+5%, TA = -40°C to +85°C1 2 3 4 5 6 7 8 9
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
tjit(Ø)
RMS Phase Jitter Random;
QCLKn = 156.25MHz
RMS Phase Jitter Random;
QCLKn = 312.5MHz
Integration Range:
12kHz – 20MHz
Integration Range:
12kHz – 20MHz
84 128 fs
66 98 fs
N(10)
Single-Side Band Noise Power,
10Hz from Carrier
QCLKn = 156.25MHz
-77 dBc/Hz
N(100)
Single-Side Band Noise Power,
100Hz from Carrier
QCLKn = 156.25MHz
-107
dBc/Hz
N(1k)
Single-Side Band Noise Power,
1kHz from Carrier
QCLKn = 156.25MHz
-124
dBc/Hz
N(10k)
Single-Side Band Noise Power,
10kHz from Carrier
QCLKn = 156.25MHz
-136
dBc/Hz
N(100k)
Single-Side Band Noise Power,
100kHz from Carrier
QCLKn = 156.25MHz
-144
dBc/Hz
N(1M)
Single-Side Band Noise Power,
1MHz from Carrier
QCLKn = 156.25MHz
-156
dBc/Hz
N(10M)
Single-Side Band Noise Power,
10MHz from Carrier
QCLKn = 156.25MHz
-160
dBc/Hz
N()
N(10)
Noise Floor (30MHz from Carrier)
Single-Side Band Noise Power,
10Hz from Carrier
QCLKn = 156.25MHz
QCLKn = 312.5MHz
-161
-67
dBc/Hz
dBc/Hz
N(100)
Single-Side Band Noise Power,
100Hz from Carrier
QCLKn = 312.5MHz
-98 dBc/Hz
N(1k)
Single-Side Band Noise Power,
1kHz from Carrier
QCLKn = 312.5MHz
-118
dBc/Hz
N(10k)
Single-Side Band Noise Power,
10kHz from Carrier
QCLKn = 312.5MHz
-130
dBc/Hz
N(100k)
Single-Side Band Noise Power,
100kHz from Carrier
QCLKn = 312.5MHz
-138
dBc/Hz
N(1M)
Single-Side Band Noise Power,
1MHz from Carrier
QCLKn = 312.5MHz
-151
dBc/Hz
N(10M)
Single-Side Band Noise Power,
10MHz from Carrier
QCLKn = 312.5MHz
-159
dBc/Hz
N()
Noise Floor (30MHz from Carrier)
QCLKn = 312.5MHz
-160
dBc/Hz
NOTE 1.Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 2.Characterized using (FX325BS) 50MHz, CL = 12pF crystal.
NOTE 3.VDD_x denotes VDD_CLK, VDD_CP, VDD_LC_IN, VDD_I2C, VDD_XTAL VDD_FB, VDD_A, VDD_A2.
NOTE 4.VSS_x denotes VSS_CP, VSS_I2C, VSS_FB, VSS_A2, VEE_A, VSS_XTAL, VEE_EP..
NOTE 5.Measured on QCLKn configured as ÷16 and ÷8.
NOTE 6.Phase noise and spurious specifications apply for device operation with QCLKn outputs active.
NOTE 7.VDD_A requires a voltage regulator. Voltage supplied to VDD_A should be derived from a regulator with a typical power supply rejection
ratio of 80dB at 1kHz and ultra low noise generation with a typical value of 3nV/Hz at 10kHz and 7nV/Hz at 1kHz.
NOTE 8.The following loop filter component values may be used: RZ = 208Ω, CZ = 4.7μF CP = 30pF. See Figure 5.
NOTE 9.The phase noise was measured up to 40MHz offset and assumed the noise floor remains same until 61.44MHz offset.
CLOCK SYNTHESIZER AND FANOUT BUFFER/DIVIDER
16
REVISION 1 11/19/14










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