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PDF ( 数据手册 , 数据表 ) D2-92684-QR

零件编号 D2-92684-QR
描述 Intelligent Digital Amplifier and Sound Processor
制造商 Intersil
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D2-92684-QR 数据手册, 描述, 功能
Intelligent Digital Amplifier and Sound Processor
D2-926xx
The D2-926xx family of the DAE-3™ and DAE-3HT™ Digital
Audio Engine™ devices are complete System-on Chip (SoC)
multi-channel digital sound processors and Class-D amplifier
controllers.
The integrated DSP provides efficient and configurable audio
signal path processing including equalization, dynamic range
compression, mixing, and filtering that is completely
configurable via the Audio Canvas™ III high level programming
interface. The integrated PWM engine supports programmable
and dynamic control of audio output, enabling a variety of
multi-channel output configurations and output power
capacity. Internal noise shaping, an embedded asynchronous
sample rate converter, dynamic level-dependent timing, and
high resolution operation supports power stage audio
performances with SNR >110dB and THD+N < 0.01%.
The D2-926xx devices are provided in two package and feature
configurations which include the 128-pin DAE-3, and the72-pin
DAE-3HT. Both the DAE-3 and DAE-3HT provide identical
performance and enable an extremely flexible platform for
feature rich and cost-affordable quality audio solutions, which
benefit from the addition of Class-D amplifiers and DSP audio
processing.
The 12 integrated digital PWM controllers can be used in a
variety of multi-channel audio system configurations,
supporting powered as well as line outputs. Fully protected
amplifier control provides efficient and clean Class-D power
output support.
Applications
• DTV and Blu-ray Soundbar
• DVD and Blu-ray Home Theater Systems
• Home Theater in a Box (HTiB)
• Audio Video Receiver (AVR)
• Multi-Channel Multi-Media (MM) Systems
• Multi-Room Distributed Audio (MRDA)
• Powered Speaker Systems
• Automotive Trunk/Amplified Solutions
Features
• Advanced DAE-3™ Digital Audio Engine™ IC Family
- DAE-3™ Pin Compatible and Function/Feature
Compatible with the D2Audio™ DAE-6™ Device Family
- DAE-3HT™ - Identical DAE-3 performance, in
72-QFN package
• Integrated DSP Digital Sound Processing
- Customizable audio path sound processing
- Fully configurable and routable audio signal paths and
hardware function assignment
- Fully Supported with Audio Canvas™ III Design Tool
• Flexible Audio Input and Output Configurations
- 12 Independent PWM Engine Channels
- 4 Independent Asynchronous I2S Digital Inputs
- Integrated high-performance stereo ADC (DAE-3 only)
- S/PDIF™ Digital Audio Inputs supporting
Linear IEC-61958 PCM or Compressed IEC-61937 Audio
- S/PDIF Digital Audio PCM Output
• Embedded 8-Channel Sample Rate Converter
• Real-Time Amplifier Control and Monitoring
- Supports Bridged, Half-Bridged, and Bridge-Tied Load (BTL)
Topologies, Using Discrete or Integrated Power Stages
- Complete Fault Protection with Automatic Recovery
• D2Audio™ SoundSuite™ Enhancement and Virtualization
• Enhanced Audio Processing Decoders And Virtualization
- Dolby® Digital/AC3
- Dolby® Pro Logic IIx
- Dolby® Virtual Speaker
- SRS TruSurround HD4™ , SRS WOW HD™,
SRS TruVolume™
July 12, 2012
FN6787.2
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2010 - 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
Dolby is a registered trademark of Dolby Laboratories. All other trademarks mentioned are the property of their respective owners.







D2-92684-QR pdf, 数据表
D2-926xx
Electrical Specifications TA = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All grounds at 0.0V. All voltages
referenced to ground. PLL at 294.912MHz, OSC at 24.576MHz, core running at 147.456MHz with typical audio data traffic. Minimum supply currents are
measured in full power down configuration. (Continued)
SYMBOL
PARAMETER
TEST
MIN
MAX
CONDITIONS
(Note 12)
TYP
(Note 12) UNIT
THD+N
- -80 - dB
Gain Mismatch
- 0.1 - dB
Crosstalk
- -80 - dB
Power Supply Rejection
- -70 - dB
NOTES:
9. All input pins except XTALI.
10. Input leakage applies to all pins except XTALO.
11. Power-down is with device in reset and clocks stopped.
12. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
13. Analog performance is system-design dependent and is affected by factors that include PCB layout, shielding and routing of analog traces, additional
components within the analog input path, and power supply isolation.
Serial Audio Interface Port Timing (Figure 1) TA = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All
grounds at 0.0V. All voltages referenced to ground.
SYMBOL
DESCRIPTION
MIN
(Note 12)
MAX
TYP (Note 12) UNIT
tcSCLK
twSCLK
tsLRCLK
thLRCLK
tsSDI
thSDI
tdSDO
SCKRx Frequency - SCKR0, SCKR1
SCKRx Pulse Width (High and Low) - SCKR0, SCKR1
LRCKRx Setup to SCLK Rising - LRCKR0, LRCKR1
LRCKRx Hold from SCLK Rising - LRCKR0, LRCKR1
SDINx Setup to SCLK Rising - SDIN0, SDIN1
SDINx Hold from SCLK Rising - SDIN0, SDIN1
SDOUTx Delay from SCLK Falling
12.5
MHz
40 ns
20 ns
20 ns
20 ns
20 ns
20 ns
tcSCLK
twSCLK
SCKRx
thLRCLK
twSCLK
LRCLKRx
tsLRCLK
tsSDI
SDINx
tdSDO
thSDI
SDOUTx
FIGURE 1. SERIAL AUDIO INTERFACE PORT TIMING
8 FN6787.2
July 12, 2012







D2-92684-QR equivalent, schematic
D2-926xx
Pin Description, DAE-3 (128-Pin) (Continued)
PIN VOLTAGE DRIVE
NAME
LEVEL STRENGTH
PIN (Note 16) TYPE
(V)
(mA)
DESCRIPTION
87 PWM6 I/O
3.3
8 or 16 PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
88 PWM5 I/O
3.3
8 or 16 PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
89 PWM4 I/O
3.3
8 or 16 PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
90 PWMVDD P
3.3
PWM output pin power. This 3.3V supply is used for the PWM pad drivers. Internally connected
to RVDD.
91 PWMGND P
3.3
PWM output pin ground. Internally connected to RGND.
92 PWM3 I/O
3.3
8 or 16 PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
93 PWM2 I/O
3.3
8 or 16 PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
94 PWM1 I/O
3.3
8 or 16 PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
95 PWM0 I/O
3.3
8 or 16 PWM output pin. (One of 18 PWM output pins. Channel and operation assignment is defined by
firmware.)
96 PWMVDD P
3.3
PWM output pin power. This 3.3V supply is used for the PWM pad drivers. Internally connected to
RVDD.
97 OSCOUT P
1.8
Analog oscillator output to slave D2-926xx devices. OSCOUT drives a buffered version of the
crystal oscillator signal from the XTALI pin.
98 PLLAGND P
1.8
PLL Analog ground
99 PLLTESTB O
1.8
Factory test use only. Must be tied low.
100 PLLTESTA O
1.8
Factory test use only. Must be tied low.
101 XTALI
P
1.8
Crystal oscillator analog input port. An external clock source would be driven into the this port. In
multi-D2-926xx systems, the OSCOUT from the master D2-926xx would drive the XTALI pin.
102 XTALO
P
1.8
Crystal oscillator analog output port. When using an external clock source, this pin must be open.
XTALO does not have a drive strength specification.
103 PLLAVDD P
1.8
PLL Analog power, 1.8V
104 ADCVDD P
3.3
Analog power for internal ADC, 3.3V
105 AIN1 I 3.3
Analog input 1 to internal ADC
106 ADCREF O
3.3
Analog voltage reference output. Must be de-coupled to analog ground with 1µF capacitor.
107 AIN0 I 3.3
Analog input 0 to internal ADC
108 ADCGND P
3.3
Analog ground for internal ADC
109 nTRST
I
3.3
Factory test only. Must be tied high at all times.
110 nCS I/O 3.3
4 SPI slave select I/O.
111 RVDD
P
3.3
Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and
receivers, except for the analog pads. Internally connected to PWMVDD.
112 RGND
P
3.3
Digital pad ring ground. Internally connected to PWMGND.
113 CGND
P
3.3
Core ground
114 CVDD
P
3.3
Core power, 1.8V
115 SC12
I/O
3.3
8 Serial Audio Interface 1, LRCK
116 SC11
I/O
3.3
8 Serial Audio Interface 1, SDAT3
16 FN6787.2
July 12, 2012










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