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PDF ( 数据手册 , 数据表 ) D2-71683-LR

零件编号 D2-71683-LR
描述 Intelligent Digital Amplifier and Sound Processor
制造商 Intersil
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D2-71683-LR 数据手册, 描述, 功能
Intelligent Digital Amplifier and Sound Processor
D2-7xx83
The D2-7xx83 family of the DAE-6™ Digital Audio Engine™
devices are complete System-on Chip (SoC) audio processor
and Class-D amplifier controllers. Integrated DSP processing
and configurable audio processing algorithms provide an
extremely flexible platform for feature rich and cost-effective
quality audio solutions which benefit from the addition of
Class-D amplifiers and DSP audio processing, meeting
demands of consumer electronics applications.
The 12 integrated digital PWM controllers can be used in a
variety of multi-channel audio system configurations,
supporting powered as well as line outputs. Fully protected
amplifier control provides efficient and clean Class-D power
output support.
The DAE-6™ device family supports full audio decoding for
formats including Dolby® Digital, Dolby® Pro Logic IIx,
AAC™ LC, DTS® Digital Surround, DTS® ES, and DTS Neo:6®.
The DAE-6 is pin-compatible and function/feature compatible
with the DAE-3™ devices, enabling additional decoding
capability to existing designs, or providing cost optimization to
lower-featured systems not requiring the additional audio
processing and decode capability.
Applications
• Audio Video Receiver (AVR)
• DTV Soundbar
• Home Theater in A Box (HTiB)
• Multi-Channel Multi-Media (MM) Systems
• Multi-Room Distributed Audio (MRDA)
• Powered Speaker Systems
• Automotive Trunk/Amplified Solutions
Features
• Advanced DAE-6™ Digital Audio Engine™ IC
- Pin Compatible and Function/Feature Compatible with
the D2Audio® DAE-3™ Device
• Total System on Chip (SoC)
- All Digital Class-D Amplifier Controller
- Full 5.1/7.1/9.1-Channel Amplifier Platform Support
• Enhanced Audio Processing Decoders
- Dolby® Digital/AC3
- Dolby® Pro Logic IIx
- AAC LC™
- DTS® Digital Surround
- DTS® ES
- DTS Neo:6®
• D2Audio® SoundSuite™ Enhancement and Virtualization
• Mark Levinson MightyCat™ Audio Enhancement
• Expanded On-Chip Memory Capacity
• Integrated DSP Processing
- 12 Channels of Digital Signal Processing (DSP) including
Equalizers, Filters, Mixers and Other Common Audio
Processing Blocks
- Fully Configurable and Routable Audio Signal Paths
• Flexible Audio Input and Output Configurations
• Embedded 8-Channel Sample Rate Converter
- Sample Rates from 32kHz up to 192kHz
• Real-Time Amplifier Control and Monitoring
- Supports Bridged, Half-Bridged, and Bridge-Tied Load
(BTL) Topologies, Using Discrete or Integrated Power
Stages from 10W to Over 500W
- Complete Fault Protection with Automatic Recovery
September 29, 2011
FN7838.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.







D2-71683-LR pdf, 数据表
D2-7xx83
Serial Audio Interface Port Timing (Figure 1) TA = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%.
All grounds at 0.0V. All voltages referenced to ground.
SYMBOL
DESCRIPTION
MIN
(Note 10)
MAX
TYP (Note 10) UNIT
tcSCLK
twSCLK
tsLRCLK
thLRCLK
tsSDI
thSDI
tdSDO
SCKRx Frequency - SCKR0, SCKR1
SCKRx Pulse Width (High and Low) - SCKR0, SCKR1
LRCKRx Setup to SCLK Rising - LRCKR0, LRCKR1
LRCKRx Hold from SCLK Rising - LRCKR0, LRCKR1
SDINx Setup to SCLK Rising - SDIN0, SDIN1
SDINx Hold from SCLK Rising - SDIN0, SDIN1
SDOUTx Delay from SCLK Falling
12.5
MHz
40 ns
20 ns
20 ns
20 ns
20 ns
20 ns
tcSCLK
twSCLK
SCKRx
thLRCLK
twSCLK
LRCLKRx
tsLRCLK
tsSDI
SDINx
tdSDO
thSDI
SDOUTx
FIGURE 1. SERIAL AUDIO INTERFACE PORT TIMING
8 FN7838.2
September 29, 2011







D2-71683-LR equivalent, schematic
D2-7xx83
Pin Descriptions (Continued)
PIN
NAME
PIN (Note 14) TYPE
VOLTAGE
LEVEL
(V)
DRIVE
STRENGTH
(mA)
DESCRIPTION
117 SC10
I/O
3.3
8 Serial Audio Interface 1, data (Assignment by firmware control.)
118 STD1
I/O
3.3
8 Serial Audio Interface 1, SDAT2
119 SCK1
I/O
3.3
8 Serial Audio Interface 1, SCK
120 SRD1
I/O
3.3
4 Serial Audio Interface 1, data (Assignment by firmware control.)
121 nRSTOUT O 3.3 16 - OD Active low open drain reset output. Pin drives low from POR generator, 3.3V brown out detector
going active, or from 1.8V brown out detector going active. This output should be used to
initiate a system reset to the nRESET pin upon brownout event detection.
122 nRESET
I
3.3
- Active low reset input with hysteresis. Activates system level reset when pulled low, initializing
all internal logic and program operations. System latches boot mode selection of the IRQ input
pins on the rising edge.
123 TIO0
I/O
3.3
16 Timer I/O port 0. Operation and assignment is controlled by firmware. Leave unconnected
when not in use.
124 PROTECT1 I/O
3.3
4 PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and
channel assignment is defined by firmware.)
125 PROTECT0 I/O
3.3
4 PWM protection input with hysteresis. (One of 9 protection inputs. Specific function and
channel assignment is defined by firmware.)
126 GPIO0
I/O
3.3
16 General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation
and assignment is defined by product application's firmware.)
127 SDA0
I/O
3.3
8 - OD
Two-Wire Serial data port 0. Bidirectional signal used by both the master and slave controllers
for data transport.
128 SCL0
I/O
3.3
8 - OD
Two-Wire Serial clock port 0. Bidirectional signal is used by both the master and slave
controllers for clock signaling.
NOTES:
14. Unless otherwise specified all pin names are active high. Those that are active low have an “n” prefix.
15. All power and ground pins of same names are to be tied together to all other pins of their same name. (i.e., CVDD pins to be tied together, CGND pins
to be tied together, RVDD pins to be tied together, and RGND pins to be tied together.) CGND and RGND are to be tied together on board. RGND and
PWMGND pins are also internally connected and are to be tied together.
16 FN7838.2
September 29, 2011










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