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PDF ( 数据手册 , 数据表 ) GV7600

零件编号 GV7600
描述 Transmitter
制造商 Semtech
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GV7600 数据手册, 描述, 功能
GV7600
Aviia™ Transmitter
Key Features
Serial digital video transmitter for standard and high
definition component video:
Š SD 525i and 625i
Š HD 720p 24, 25, 30, 50 and 60
Š HD 1080i 50, 60
Š HD 1080p 24, 25, 30, 50 and 60
Supports 8-bit, 10-bit or 12-bit component digital
video:
Š RGB or YCbCr 4:4:4 sampled
Š YCbCr 4:2:2 or 4:2:0 sampled
Single 75Ω coaxial cable driver output
Integrated audio embedder for the carriage of up to 8
channels of 48kHz digital audio
Asynchronous Serial Interface (ASI) for transmission of
IEC 13818-1 compliant transport streams
Ancillary (ANC) data insertion
User selectable processing features, including:
Š Timing Reference Signal (TRS) insertion
Š Programmable ANC data insertion
Š Illegal video code word re-mapping
4-wire Gennum Serial Peripheral Interface (GSPI) for
external host command and control
Dedicated JTAG test interface
1.2V core and 3.3V analog voltage power supplies
1.8V or 3.3V selectable digital I/O power supply
Small footprint 100-BGA (11mm x 11mm)
Low power operation, typically 400mW
Pb-free and RoHS compliant
Applications
Industrial & professional cameras
Digital video recorders (DVR)
Video servers
Video mixers and switchers
Camcorders
Description
The GV7600 is a serial digital video transmitter for standard
and high definition component video. With integrated
cable driving technology, the GV7600 is capable of
transmitting digital video at 270Mb/s, 1.485Gb/s and
2.97Gb/s over 75Ω coaxial cable. The device provides a
complete transmit solution for the transmission of both
interlaced and progressive component digital video, up to
1920 x 1080, in coaxial cable-based video systems.
Using the GV7600 with the complete Aviia transmitter
reference design, it is possible to implement an all-digital,
bi-directional multimedia interface over coax. This
interface allows both DC power and a bi-directional,
half-duplex, auxiliary data interface, up to 1Mb/s, to be
carried over the same single, robust and cost effective
coaxial cable as the high-speed serial digital video.
The GV7600 includes a broad range of user-selectable
processing features, such as Timing Reference Signal (TRS)
insertion, illegal code word re-mapping, and ancillary data
packet insertion. The content of ancillary data packets can
be programmed via the host interface. Device
configuration and status reporting is accomplished via the
Gennum Serial Peripheral Interface (GSPI). Alternatively,
many processing features and operational modes can be
configured directly through external pin settings.
The device supports both 8-bit, 10-bit and 12-bit video data
input, for RGB or YCbCr 4:4:4, and YCbCr 4:2:2 or 4:2:0. A
configurable 20-bit wide parallel digital video input bus is
provided, with associated pixel clock and timing signal
inputs. The GV7600 supports direct interfacing of ITU-R
BT.656 SD formats, and HD formats conforming to ITU-R
BT.709 and BT.1120-6 for 1125-line formats, and SMPTE
296M for 750-line formats. The device may also be
configured to accepts CEA-861 timing.
The GV7600 audio embedding function allows the carriage
of up to 8 channels of serial digital audio within the
ancillary data space of the video data stream. The input
audio signal formats supported by the device include
AES/EBU for professional applications, S/PDIF, and I2S.
16-bit, 20-bit and 24-bit audio formats are supported at
GV7600
Final Data Sheet
GENDOC-051686
Rev.8
April 2014
www.semtech.com
1 of 123
Proprietary & Confidential







GV7600 pdf, 数据表
Figure 4-33: H:V:DE Input Timing 720 (1440) x 576 @ 50 (Format 21 & 22) ................................. 59
Figure 4-34: H:V:DE Timing 1920 x 1080p @ 59.94/60 (Format 16) ................................................ 60
Figure 4-35: H:V:DE Timing 1920 x 1080p @ 50 (Format 31) ............................................................ 61
Figure 4-36: H:V:DE Timing 1920 x 1080p @ 23.94/24 (Format 32) ................................................ 62
Figure 4-37: H:V:DE Timing 1920 x 1080p @ 25 (Format 33) ............................................................ 63
Figure 4-38: H:V:DE Timing 1920 x 1080p @ 29.97/30 (Format 34) ................................................ 64
Figure 4-39: ACLK to Data and Control Signal Input Timing ............................................................ 66
Figure 4-40: I2S Audio Input Format .......................................................................................................... 67
Figure 4-41: AES/EBU or S/PDIF Audio Input Format .......................................................................... 68
Figure 4-42: Serial Audio, Left Justified, MSB First ............................................................................... 68
Figure 4-43: Serial Audio, Left Justified, LSB First ................................................................................. 68
Figure 4-44: Serial Audio, Right Justified, MSB First ............................................................................ 68
Figure 4-45: Serial Audio, Right Justified, LSB First .............................................................................. 68
Figure 4-46: Ancillary Data Packet Placement Example ..................................................................... 70
Figure 4-47: Ancillary Data Packets ........................................................................................................... 76
Figure 4-48: ORL Matching Network, BNC and Coaxial Cable Connection ................................. 87
Figure 4-49: GSPI Application Interface Connection ........................................................................... 89
Figure 4-50: Command Word Format ....................................................................................................... 90
Figure 4-51: Data Word Format ................................................................................................................... 90
Figure 4-52: Write Mode ................................................................................................................................ 91
Figure 4-53: Read Mode ................................................................................................................................. 91
Figure 4-54: GV7600 GSPI Timing Delays ................................................................................................ 91
Figure 4-55: Reset Pulse ...............................................................................................................................116
Figure 6-1: GV7600 Package Dimensions ..............................................................................................118
Figure 6-2: GV7600 Marking Diagram ....................................................................................................119
Figure 6-3: Pb-free Solder Reflow Profile ...............................................................................................120
GV7600
Final Data Sheet
GENDOC-051686
Rev.8
April 2014
www.semtech.com
8 of 123
Proprietary & Confidential







GV7600 equivalent, schematic
Table 1-1: Pin Descriptions (Continued)
Pin
Number
J6
J7
Name
AIN1/2
WCLK1
Timin
g
Type
Input
Input
J8 TCK
Input
J9 SDOUT
Output
J10 SCLK
K4 AIN7/8
K5 ACLK2
K6 AIN3/4
K7 ACLK1
K9
CS
K10 SDIN
Input
Input
Input
Input
Input
Input
Input
Description
Serial Audio Input; Channels 1 and 2.
48kHz Word clock for Channels 1-4.
COMMUNICATION SIGNAL INPUT.
Signal levels are LVCMOS/LVTTL compatible.
JTAG Serial Data Clock Signal.
This pin is the JTAG clock.
COMMUNICATION SIGNAL OUTPUT.
Signal levels are LVCMOS / LVTTL compatible.
Serial Data Output.
This pin operates as the host interface serial output, used to read
status and configuration information from the internal registers of
the device.
IO_VDD = 3.3V
Drive Strength = 12mA
IO_VDD = 1.8V
Drive Strength = 4mA
COMMUNICATION SIGNAL INPUT.
Signal levels are LVCMOS / LVTTL compatible.
Serial data clock signal.
SCLK operates as the host interface burst clock, SCLK. Command
and data read/write words are clocked into the device
synchronously with this clock.
Note: If the host interface is not being used, tie this pin HIGH.
Serial Audio Input; Channels 7 and 8.
64 x WCLK for Channels 5-8.
Serial Audio Input; Channels 3 and 4.
64 x WCLK for Channels 1-4.
COMMUNICATION SIGNAL INPUT.
Signal levels are LVCMOS / LVTTL compatible.
Chip select.
CS operates as the host interface Chip Select, and is active LOW.
COMMUNICATION SIGNAL INPUT.
Signal levels are LVCMOS / LVTTL compatible.
Serial data in.
This pin is used to write address and configuration data words into
the device.
GV7600
Final Data Sheet
GENDOC-051686
Rev.8
April 2014
www.semtech.com
16 of 123
Proprietary & Confidential










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