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零件编号 | MTV32N25E | ||
描述 | Power Field Effect Transistor | ||
制造商 | ON Semiconductor | ||
LOGO | |||
1 Page
MTV32N25E
Designer’s™ Data Sheet
TMOS E−FET.™
Power Field Effect
Transistor
D3PAK for Surface Mount
N−Channel Enhancement−Mode Silicon
Gate
The D3PAK package has the capability of housing the largest chip
size of any standard, plastic, surface mount power semiconductor. This
allows it to be used in applications that require surface mount
components with higher power and lower RDS(on) capabilities. This
high voltage MOSFET uses an advanced termination scheme to provide
enhanced voltage−blocking capability without degrading performance
over time. In addition, this advanced TMOS E−FET is designed to
withstand high energy in the avalanche and commutation modes. The
new energy efficient design also offers a drain−to−source diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in surface mount PWM motor controls and both ac−dc and
dc−dc power supplies. These devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating areas
are critical and offer additional safety margin against unexpected
voltage transients.
• Robust High Voltage Termination
• Avalanche Energy Specified
• Source−to−Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
• Short Heatsink Tab Manufactured − Not Sheared
• Specifically Designed Leadframe for Maximum Power Dissipation
• Available in 24 mm, 13−inch/500 Unit Tape & Reel, Add −RL Suffix
to Part Number
http://onsemi.com
TMOS POWER FET
32 AMPERES, 250 VOLTS
RDS(on) = 0.08 W
D3PAK Surface Mount
CASE 433−01
Style 2
D
N−Channel
®G
S
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 1
1
Publication Order Number:
MTV32N25E/D
MTV32N25E
INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.190
4.826
0.165
4.191
0.100
2.54
0.118
3.0
0.063
1.6
0.243
6.172
inches
mm
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
The power dissipation for a surface mount device is a
function of the drain pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a surface
mount device is determined by TJ(max), the maximum rated
junction temperature of the die, RθJA, the thermal resistance
from the device junction to ambient, and the operating
temperature, TA. Using the values provided on the data
sheet, PD can be calculated as follows:
PD =
TJ(max) − TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device. For a D3PAK
device, PD is calculated as follows.
PD =
150°C − 25°C = 2.0 Watts
62.5°C/W
The 62.5°C/W for the D3PAK package assumes the use of
the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 2.0 Watts. There are
other alternatives to achieving higher power dissipation from
the surface mount packages. One is to increase the area of
the drain pad. By increasing the area of the drain pad, the
power dissipation can be increased. Although one can
almost double the power dissipation with this method, one
will be giving up area on the printed circuit board which can
defeat the purpose of using surface mount technology. For
example, a graph of RθJA versus drain pad area is shown in
Figure 15.
100
Board Material = 0.0625″
G−10/FR−4, 2 oz Copper
1.75 Watts
80
TA = 25°C
60
3.0 Watts
40
5.0 Watts
20
0 2 4 6 8 10
A, AREA (SQUARE INCHES)
Figure 16. Thermal Resistance versus Drain Pad
Area for the D3PAK Package (Typical)
Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad™. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
http://onsemi.com
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页数 | 11 页 | ||
下载 | [ MTV32N25E.PDF 数据手册 ] |
零件编号 | 描述 | 制造商 |
MTV32N25E | Power Field Effect Transistor | ON Semiconductor |
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