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PDF ( 数据手册 , 数据表 ) NOIV1SN016KA

零件编号 NOIV1SN016KA
描述 VITA 16/12 MegaPixels Single Foot Print CMOS Image Sensor
制造商 ON Semiconductor
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NOIV1SN016KA 数据手册, 描述, 功能
NOIV1SN016KA,
NOIV1SN012KA
VITA 16/12 MegaPixels
Single Foot Print CMOS
Image Sensor
www.onsemi.com
Features
Active Pixel Array:
16K = 4096 × 4096 Active Pixels
12K = 4096 × 3072 Active Pixels
Optical Format:
16K = APSC Optical Format
12K = 4/3 inch Optical Format
4.5 mm × 4.5 mm Square Pixels
32/16 Low-Voltage Differential Signaling (LVDS) High-speed
Serial Outputs
VITA 16K Frame Rate at Full Resolution, 32 LVDS Outputs
80 Frames per Second normal ROT
125 Frames per Second Zero ROT
VITA 12K Frame Rate at Full Resolution, 32 LVDS Outputs
110 Frames per Second normal ROT
160 Frames per Second Zero ROT
Monochrome (SN), Color (SE)
On-chip 10-bit Analog-to-Digital Converter (ADC)
Figure 1. VITA 16K/12K Photograph
8-bit or 10-bit Output Mode
32 Random Programmable Region of Interest (ROI)
readout
Applications
Pipelined and Triggered Global Shutter, Rolling Shutter
Machine Vision
Serial Peripheral Interface (SPI)
Motion Monitoring
Operational Temperature Range: -40°C to +85°C
Intelligent Traffic Systems (ITS)
Single 355pin mPGA package across resolutions
Pick and Place Machines
Power Dissipation: 4.1 W @ 2 Gpix/s
Inspection
These Devices are PbFree and are RoHS Compliant
Metrology
Description
The high-resolution VITA CMOS image sensor family features global and rolling shutter mode. The on-chip programmable
state machine controls the sensor array and enables high flexibility with changes in operation modes and 32 frame-to-frame
configurable Regions-of-Interest (ROI). The 5T pixel on a 4.5 mm pitch enables pipelining of integration and read-out in both
triggered and un-triggered global shutter mode.
A second pipeline stage provides a maximum frame rate increase by allowing the sensor to run in Zero-ROT mode. The roller
shutter mode supports correlated double sampling, reducing temporal noise by approximately 3 dB. The sensor has on-chip
programmable gain amplifiers and 10-bit A/D converters. The image’s black level has an automatic calibration with adjustable
user programmable offset. The image data interface consists of 32 or 16 LVDS channels with additional clock and
synchronization channels in parallel, each running at 680 Mbps.
The high-resolution VITA family is packaged in a ceramic 355-pin PGA package and is available in a monochrome and color
version.
Contact your local ON Semiconductor office for more information.
© Semiconductor Components Industries, LLC, 2015
May, 2015 Rev. 0
1
Publication Order Number:
NOIV1SN016KA/D







NOIV1SN016KA pdf, 数据表
NOIV1SN016KA, NOIV1SN012KA
OVERVIEW
Figure 5 gives an overview of all functional blocks in the
image sensor. The system clock is received by the LVDS
clock receiver block and distributed to other blocks. The
sequencer defines the sensor timing and controls the image
core. The sequencer is started either autonomously (master
mode) or on assertion of an external trigger (slave mode).
The image core contains all pixels and readout circuits. The
column structure selects pixels for readout and performs
correlated double sampling (CDS) or double sampling (DS).
The data comes out sequentially and is fed into the analog
front end (AFE) block. The programmable gain amplifier
(PGA) of the AFE adds the offset and gain. The output is a
fully differential analog signal that goes to the ADC, where
the analog signal is converted to a 10-bit data stream.
Depending on the operating mode, eight or ten bits are fed
into the data formatting block. This block adds
synchronization information to the data stream based on the
frame timing. The data then goes to the low voltage serial
(LVDS) interface block that sends the data out through the
I/O ring.
On-chip programmability is controlled through the Serial
Peripheral Interface (SPI). See Register Map on page 45 for
register details. A bias block generates bias currents and
voltages for all analog blocks on the chip. By controlling the
bias current, the speed-versus-power of each block can be
tuned. All biasing programmability is contained in the bias
block.
Image Core Bias
Image Core
Pixel Array
Control & Registers
LVDS Clock
Receiver
SPI Reset
Interface
Column Structure
64 Analog Channels
Analog Front End (AFE)
64 x 10-bit
Digital Channels
Data Formatting
32 x 10-bit
Digital Channels
Serializers & LVDS Interface
Biasing &
Bandgap
External
Resistor
32/16 Multiplexed LVDS Output Channels
1 LVDS Sync Channel
1 LVDS Clock Channel
Figure 5. Block Diagram
www.onsemi.com
8







NOIV1SN016KA equivalent, schematic
NOIV1SN016KA, NOIV1SN012KA
Required Register Uploads
In this phase the ’reserved’ register settings are uploaded
through the SPI register. Different settings are not allowed
and may cause the sensor to malfunction. The required
uploads are listed in Table 10.
Table 10. REQUIRED REGISTER UPLOADS
No. Address Data
Description
1 65 0x008B General Biasing
2 66 0x53C8 AFE Biasing
3 67 0x8848 Mux Biasing
4 68 0x0086 LVDS Biasing
5 128 0x4520 Set desired output level to code
32 for 10-bit mode, code 8 for
8-bit mode.
Set number of samples for
black calibration to 25.
6 204 0x09E5 Configure unity gain
(Normal ROT)
0x09E6 Configure unity gain
(Zero ROT)
7 224 0x3E04 Dummy rows upon integration
start
8 225 0x6733 Configure internal latency
9 129[13]
0x0 10-bit Mode
0x1 8-bit Mode
10 447 0x0BF1 Configure sequencer
11 448 0x0BC3 Configure sequencer
12 256 0x4708 Configure ROI (x)
13 257 0x0200 Configure ROI (y) 16K res.
0x0400 Configure ROI (y) 12K res.
14 258 0x11FF Configure ROI (y) 16K res.
0x0FFF Configure ROI (y) 12K res.
Soft Power Up
During the soft power-up action, the internal blocks are
enabled and prepared to start processing the image data
stream. This action exists of a set of SPI uploads. The soft
power-up uploads are listed in Table 11.
Table 11. SOFT POWER UP REGISTER UPLOADS
No. Address Data
Description
1 32 0x2003 Enable Analog Clock Distribu-
tion
2 64 0x0001 Enable Biasing Block
3 40 0x0003 Enable Column Multiplexer
4 48 0x0001 Enable Analog Front-End
(AFE)
5 112 0x0007 Enable LVDS Transmitters
Enable Sequencer
During the ‘Enable Sequencer’-action, the frame
grabbing sequencer is enabled. The sensor will start
grabbing images in the configured operation mode. Refer to
Operating Modes on page 10 for an overview of the possible
operation modes.
The ‘Enable Sequencer’ action consists of a set op register
uploads. The required uploads are listed in Table 12.
Table 12. ENABLE SEQUENCER REGISTER
UPLOADS
No. Address Data (Normal ROT) Data (Zero ROT)
1 192
0x0001
0x000D
User Actions: Functional Mode to Power Down
Sequences
Disable Sequencer
During the ‘Disable Sequencer’-action, the frame
grabbing sequencer is stopped. The sensor will stop
grabbing images and returns to the idle mode.
The ‘Disable Sequencer’ action consists of a set op
register uploads. The required uploads are listed in Table 13.
Table 13. DISABLE SEQUENCER REGISTER
UPLOADS
No. Address Data
Description
1 192[0]
0x0 Disable of Sequencer.
NOTE: This address contains
other configuration bits to se-
lect the operation mode.
Soft Power Down
During the soft power-down action, the internal blocks are
disabled and the sensor is put in standby state in order to
reduce the current dissipation. This action exists of a set of
register uploads. The soft power-down uploads are listed in
Table 14.
Table 14. SOFT POWER DOWN REGISTER UPLOADS
No. Address Data
Description
1 112 0x0000 Disable LVDS Transmitters
2 48 0x0000 Disable Analog Front-End
(AFE)
3 40 0x0000 Disable Column Multiplexer
4 64 0x0000 Disable Biasing Block
5 32 0x2002 Disable Analog Clock Distribu-
tion
www.onsemi.com
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