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PDF ( 数据手册 , 数据表 ) 5P49V5907

零件编号 5P49V5907
描述 Programmable Clock Generator
制造商 Integrated Device Technology
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5P49V5907 数据手册, 描述, 功能
Programmable Clock Generator
5P49V5907
DATASHEET
Description
The 5P49V5907 is a programmable clock generator intended
for high performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I2C
interface. This is IDTs fifth generation of programmable clock
technology (VersaClock® 5).
The frequencies are generated from a single reference clock
or crystal. Two select pins allow up to 4 different
configurations to be programmed and accessible using
processor GPIOs or bootstrapping. The different selections
may be used for different operating modes (full function,
partial function, partial power-down), regional standards (US,
Japan, Europe) or system production margin testing.
The device may be configured to use one of two I2C
addresses to allow multiple devices to be used in a system.
Pin Assignment
NC
XOUT
XIN/REF
VDDA
VDDO
OUT7
OUT7B
OUT6
OUT6B
SD/OE
40 39 38 37 36 35 34 33 32 31
1 30
2 29
3 28
4 27
5 26
EPAD
6 25
7 24
8 23
9 22
10 21
11 12 13 14 15 16 17 18 19 20
VDDO2
OUT2
OUT2B
VDD
VDD
VDD_CORE
OUT3
OUT3B
NC
NC
40-pin VFQFPN
Features
Generates up to four independent output frequencies with a
total of 7 differential outputs and one reference output
Supports multiple differential output I/O standards:
– Three universal outputs pairs with each configurable
as one differential output pair (LVDS, LVPECL or
regular HCSL) or two LVCMOS outputs. Frequency of
each output pair can be individually programmed
– Four copies of Low Power HCSL(LP-HCSL) outputs.
Programmable frequency:
– See Output Features and Descriptions for details
One reference LVCMOS output clock
High performance, low phase noise PLL, <0.7 ps RMS
typical phase jitter on outputs:
– PCIe Gen1, 2, 3 compliant clock capability
– USB 3.0 compliant clock capability
– 1 GbE and 10 GbE
Four fractional output dividers (FODs)
Independent Spread Spectrum capability from each
fractional output divider (FOD)
Four banks of internal non-volatile in-system
programmable or factory programmable OTP memory
I2C serial programming interface
Input frequency ranges:
– LVCMOS Reference Clock Input (XIN/REF) – 1MHz
to 200MHz
– Crystal frequency range: 8MHz to 40MHz
Output frequency ranges:
– LVCMOS Clock Outputs – 1MHz to 200MHz
– LP-HCSL Clock Outputs – 1MHz to 200MHz
– Other Differential Clock Outputs – 1MHz to 350MHz
Programmable loop bandwidth
Programmable crystal load capacitance
Power-down mode
Mixed voltage operation:
– 1.8V core
– 1.8V VDDO for 4 LP-HCSL outputs
– 1.8V to 3.3V VDDO for other outputs
(3 programmable differential outputs and 1 reference
output)
– See Pin Descriptions for details
Packaged in 40-pin 5mm x 5mm VFQFPN (NDG40)
-40° to +85°C industrial temperature operation
5P49V5907 REVISION B 07/13/15
1
©2015 Integrated Device Technology, Inc.







5P49V5907 pdf, 数据表
5P49V5907 DATASHEET
I2C Mode Operation
The device acts as a slave device on the I2C bus using one of
the two I2C addresses (0xD0 or 0xD4) to allow multiple
devices to be used in the system. The interface accepts
byte-oriented block write and block read operations. Two
address bytes specify the register address of the byte position
of the first register to write or read. Data bytes (registers) are
accessed in sequential order from the lowest to the highest
byte (most significant bit first). Read and write block transfers
can be stopped after any complete byte transfer. During a
write operation, data will not be moved into the registers until
the STOP bit is received, at which point, all data received in
the block write will be written simultaneously.
For full electrical I2C compliance, it is recommended to use
external pull-up resistors for SDATA and SCLK. The internal
pull-down resistors have a size of 100ktypical.
Current Read
S Dev Addr + R A Data 0 A Data 1 A
A
Data n
Abar P
Sequential Read
S Dev Addr + W A Reg start Addr A Sr Dev Addr + R A Data 0 A Data 1 A
A
Sequential Write
S
Dev Addr + W
A
Reg start Addr
A
Data 0
A
Data 1
A
A Data n A P
Data n
Abar P
from master to slave
from slave to master
S = start
Sr = repeated start
A = acknowledge
Abar= none acknowledge
P = stop
I2C Slave Read and Write Cycle Sequencing
PROGRAMMABLE CLOCK GENERATOR
8
REVISION B 07/13/15







5P49V5907 equivalent, schematic
5P49V5907 DATASHEET
Table 20: AC Timing Electrical Characteristics (VDDO = 1.8V ±5%, TA = -40°C to +85°C)
(Spread Spectrum Generation = OFF)
Symbol Parameter
fIN 1 Input Frequency
fOUT Output Frequency
fVCO VCO Frequency
fPFD PFD Frequency
fBW Loop Bandwidth
t2 Input Duty Cycle
t3 Output Duty Cycle
Slew Rate, SLEW[1:0] = 00
Slew Rate, SLEW[1:0] = 01
Slew Rate, SLEW[1:0] = 10
Slew Rate, SLEW[1:0] = 11
Slew Rate, SLEW[1:0] = 00
t4
Slew Rate, SLEW[1:0] = 01
Slew Rate, SLEW[1:0] = 10
Slew Rate, SLEW[1:0] = 11
Slew Rate, SLEW[1:0] = 00
Slew Rate, SLEW[1:0] = 01
Slew Rate, SLEW[1:0] = 10
Slew Rate, SLEW[1:0] = 11
Rise Times
t5
Fall Times
Rise Times
Fall Times
Test Conditions
Input frequency limit (XIN)
Input frequency limit (REF)
Single ended clock output limit (LVCMOS)
Differential clock output limit
VCO operating frequency range
PFD operating frequency range
Input frequency = 25MHz
Duty Cycle
All differential outputs except Reference
output
Measured at VDD/2, all outputs except
Reference output 2.5V and 3.3V
Measured at VDD/2, all outputs except
Reference output 1.8V
Measured at VDD/2, Reference output
(150.1MHz - 200MHz) with 50% input
Measured at VDD/2, Reference output(s)
(120.1MHz - 200MHz)
Single-ended 3.3V LVCMOS output clock
rise and fall time, 20% to 80% of VDDO
(Output Load = 5 pF) VDD=3.3V
Single-ended 3.3V LVCMOS output clock
rise and fall time, 20% to 80% of VDDO
(Output Load = 5 pF) VDD=2.5V
Single-ended 3.3V LVCMOS output clock
rise and fall time, 20% to 80% of VDDO
(Output Load = 5 pF) VDD=1.8V
LVDS, 20% to 80%
LVDS, 80% to 20%
LVPECL, 20% to 80%
LVPECL, 80% to 20%
Min.
8
1
1
1
2500
11
0.06
45
45
45
40
40
30
1.5
1.3
1.2
1.0
1.0
0.8
0.7
0.6
1.5
1.3
1.2
1.0
Typ.
2800
50
50
50
50
50
2.6
2.4
2.3
2.2
1.7
1.5
1.4
1.3
2.6
2.4
2.3
2.2
300
300
400
400
Max.
40
200
200
350
3000
150
0.9
55
55
55
60
60
70
4.0
3.8
3.7
3.6
2.7
2.5
2.45
2.39
4.0
3.8
3.75
3.67
Units
MHz
MHz
MHz
MHz
MHz
MHz
%
%
%
%
%
%
V/ns
ps
PROGRAMMABLE CLOCK GENERATOR
16
REVISION B 07/13/15










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