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PDF ( 数据手册 , 数据表 ) 5P49V5901

零件编号 5P49V5901
描述 Programmable Clock Generator
制造商 Integrated Device Technology
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5P49V5901 数据手册, 描述, 功能
Programmable Clock Generator
5P49V5901
DATASHEET
Description
Features
The 5P49V5901 is a programmable clock generator intended
for high performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I2C
interface. This is IDTs fifth generation of programmable clock
technology (VersaClock® 5).
The frequencies are generated from a single reference clock.
The reference clock can come from one of the two redundant
clock inputs. A glitchless manual switchover function allows
one of the redundant clocks to be selected during normal
operation.
Two select pins allow up to 4 different configurations to be
programmed and accessible using processor GPIOs or
bootstrapping. The different selections may be used for
different operating modes (full function, partial function, partial
power-down), regional standards (US, Japan, Europe) or
system production margin testing.
The device may be configured to use one of two I2C
addresses to allow multiple devices to be used in a system.
Pin Assignment
CLKIN
CLKINB
XOUT
XIN/REF
VDDA
CLKSEL
1 24 23
22
21
20
19
18
2 17
3 16
4
EPAD
15
5 14
6 13
7 8 9 10 11 12
VDDO2
OUT2
OUT2B
VDDO3
OUT3
OUT3B
24-pin VFQFPN
Generates up to four independent output frequencies
High performance, low phase noise PLL, <0.7 ps RMS
typical phase jitter on outputs:
– PCIe Gen1, 2, 3 compliant clock capability
– USB 3.0 compliant clock capability
– 1 GbE and 10 GbE
Four fractional output dividers (FODs)
Independent Spread Spectrum capability on each output
pair
Four banks of internal non-volatile in-system
programmable or factory programmable OTP memory
I2C serial programming interface
One reference LVCMOS output clock
Four universal output pairs:
– Each configurable as one differential output pair or two
LVCMOS outputs
I/O Standards:
– Single-ended I/Os: 1.8V to 3.3V LVCMOS
– Differential I/Os - LVPECL, LVDS and HCSL
Input frequency ranges:
– LVCMOS Reference Clock Input (XIN/REF) – 1MHz to
200MHz
– LVDS, LVPECL, HCSL Differential Clock Input (CLKIN,
CLKINB) – 1MHz to 350MHz
– Crystal frequency range: 8MHz to 40MHz
Output frequency ranges:
– LVCMOS Clock Outputs – 1MHz to 200MHz
– LVDS, LVPECL, HCSL Differential Clock Outputs –
1MHz to 350MHz
Individually selectable output voltage (1.8V, 2.5V, 3.3V) for
each output pair
Redundant clock inputs with manual switchover
Programmable loop bandwidth
Programmable output to output skew
Programmable slew rate control
Programmable crystal load capacitance
Individual output enable/disable
Power-down mode
1.8V, 2.5V or 3.3V core VDDD, VDDA
Available in 24-pin VFQFPN 4mm x 4mm package
-40° to +85°C industrial temperature operation
5P49V5901 NOVEMBER 11, 2016
1 ©2016 Integrated Device Technology, Inc.







5P49V5901 pdf, 数据表
5P49V5901 DATASHEET
OTP Interface
The 5P49V5901 can also store its configuration in an internal
OTP. The contents of the device's internal programming
registers can be saved to the OTP by setting burn_start
(W114[3]) to high and can be loaded back to the internal
programming registers by setting usr_rd_start(W114[0]) to
high.
To initiate a save or restore using I2C, only two bytes are
transferred. The Device Address is issued with the read/write
bit set to “0”, followed by the appropriate command code. The
save or restore instruction executes after the STOP condition
is issued by the Master, during which time the 5P49V5901 will
not generate Acknowledge bits. The 5P49V5901 will
acknowledge the instructions after it has completed execution
of them. During that time, the I2C bus should be interpreted as
busy by all other users of the bus.
On power-up of the 5P49V5901, an automatic restore is
performed to load the OTP contents into the internal
programming registers. The 5P49V5901 will be ready to
accept a programming instruction once it acknowledges its
7-bit I2C address.
Availability of Primary and Secondary I2C addresses to allow
programming for multiple devices in a system. The I2C slave
address can be changed from the default 0xD4 to 0xD0 by
programming the I2C_ADDR bit D0. VersaClock 5
Programming Guide provides detailed I2C programming
guidelines and register map.
SD/OE Pin Function
The polarity of the SD/OE signal pin can be programmed to be
either active HIGH or LOW with the SP bit (W16[1]). When SP
is “0” (default), the pin becomes active LOW and when SP is
“1”, the pin becomes active HIGH. The SD/OE pin can be
configured as either to shutdown the PLL or to enable/disable
the outputs. The SH bit controls the configuration of the
SD/OE pin The SH bit needs to be high for SD/OE pin to be
configured as SD.
SP
SD/OE Input
SH
OEn
Global Shutdown
OSn
OUTn
When configured as SD, device is shut down, differential
outputs are driven High/low, and the single-ended LVCMOS
outputs are driven low. When configured as OE, and outputs
are disabled, the outputs are driven high/low.
Table 5: SD/OE Pin Function Truth Table
SH bit SP bit OSn bit OEn bit SD/OE
OUTn
00
0
x
x Tri-state2
00
1
0 x Output active
00
1
1 0 Output active
00
1
1 1 Output driven High Low
01
0
x
x Tri-state2
01
1
0 x Output active
01
1
1 0 Output driven High Low
01
1
1 1 Output active
10
0
x
0 Tri-state2
10
1
0 0 Output active
10
1
1 0 Output active
11
0
x
0 Tri-state2
11
1
0 0 Output active
11
1
1 0 Output driven High Low
1x
x
x 1 Output driven High Low 1
Note 1 : Global Shutdown
Note 2 : Tri-state regardless of OEn bits
Output Divides
Each output divide block has a synchronizing POR pulse to
provide startup alignment between outputs divides. This
allows alignment of outputs for low skew performance. This
low skew would also be realized between outputs that are
both integer divides from the VCO frequency. This phase
alignment works when using configuration with SEL1, SEL0.
For I2C programming, I2C reset is required.
An output divide bypass mode (divide by 1) will also be
provided, to allow multiple buffered reference outputs.
Each of the four output divides are comprised of a 12 bit
integer counter, and a 24 bit fractional counter. The output
divide can operate in integer divide only mode for improved
performance, or utilize the fractional counters to generate a
clock frequency accurate to 50 ppb.
Each of the output divides also have structures capable of
independently generating spread spectrum modulation on the
frequency output.
The Output Divide also has the capability to apply a spread
modulation to the output frequency. Independent of output
frequency, a triangle wave modulation between 30 and 63kHz
may be generated.
For all outputs, there is a bypass mode, to allow the output to
behave as a buffered copy of the input.
PROGRAMMABLE CLOCK GENERATOR
8
NOVEMBER 11, 2016







5P49V5901 equivalent, schematic
5P49V5901 DATASHEET
Table 19:DC Electrical Characteristics for LVPECL (VDDO = 3.3V+5% or 2.5V+5%, TA = -40°C to
+85°C)
Symbol
Parameter
VOH
VOL
VSWING
Output Voltage HIGH, terminated through 50tied to VDD - 2 V
Output Voltage LOW, terminated through 50tied to VDD - 2 V
Peak-to-Peak Output Voltage Swing
Min Typ Max Unit
VDDO - 1.19
VDDO - 1.94
0.55
VDDO - 0.69
VDDO - 1.4
0.993
V
V
V
Table 20:Electrical Characteristics – DIF 0.7V HCSL Differential Outputs (VDDO = 3.3V±5%,
2.5V±5%, TA = -40°C to +85°C)
Symbol Parameter
Conditions
Min Typ Max Units Notes
dV/dt Slew Rate
Scope averaging on
1 4 V/ns 1,2,3
ΔdV/dt
VHIGH
VLOW
Slew Rate
Voltage High
Voltage Low
Scope averaging on
Statistical measurement on single-ended
signal using oscilloscope math function
(Scope averaging ON)
660
-150
20 % 1,2,3
850 mV 1,6,7
150 mV 1,6
VMAX Maximum Voltage
VMIN Minimum Voltage
Measurement on single-ended signal using
absolute value (Scope averaging off)
-300
1150
mV
mV
1
1
VSWING Voltage Swing
Scope averaging off
300 mV 1,2,6
VCROSS Crossing Voltage Value Scope averaging off
250 550 mV 1,4,6
ΔVCROSS Crossing Voltage variation Scope averaging off
140 mV 1,5
1. Guaranteed by design and characterization. Not 100% tested in production
2. Measured from differential waveform.
3. Slew rate is measured through the VSWING voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4. VCROSS is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge
(i.e. Clock rising and Clock# falling).
5. The total variation of all VCROSS measurements in any particular system. Note that this is a subset of VCROSS min/max (VCROSS absolute)
allowed. The intent is to limit VCROSS induced modulation by setting VCROSS to be smaller than VCROSS absolute.
6. Measured from single-ended waveform.
7. Measured with scope averaging off, using statistics function. Variation is difference between min. and max.
PROGRAMMABLE CLOCK GENERATOR
16
NOVEMBER 11, 2016










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