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PDF ( 数据手册 , 数据表 ) LE25U40CMD

零件编号 LE25U40CMD
描述 4M-bit (512K x 8) Serial Flash Memory
制造商 ON Semiconductor
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LE25U40CMD 数据手册, 描述, 功能
LE25U40CMD
CMOS LSI
4M-bit (512K x 8)
Serial Flash Memory
www.onsemi.com
Overview
The LE25U40CMD is a SPI bus flash memory device with a 4M bit (512K
8-bit) configuration that adds a high performance Dual output and Dual I/O
function. It uses a single 2.5V power supply. While making the most of the
features inherent to a serial flash memory device, the LE25U40CMD is
housed in an 8-pin ultra-miniature package. All these features make this
device ideally suited to storing program in applications such as portable
information devices, which are required to have increasingly more compact
dimensions. The LE25U40CMD also has a small sector erase capability
which makes the device ideal for storing parameters or data that have fewer
rewrite cycles and conventional EEPROMs cannot handle due to insufficient
capacity.
SOIC 8, 150mils
Features
Read/write operations enabled by single 2.5V power supply : 2.3 to 3.6V supply voltage range
Operating frequency : 40MHz
Temperature range
: 40 to 85C
Serial interface
: SPI mode 0, mode 3 supported / Dual Output, Dual I/O supported
Sector size
: 4K bytes/small sector, 64K bytes/sector
Small sector erase, sector erase, chip erase functions
Page program function (256 bytes / page)
Block protect function
Highly reliable read/write
Number of rewrite times : 100,000 times
Small sector erase time : 40ms (typ), 150ms (max)
Sector erase time
: 80ms (typ), 250ms (max)
Chip erase time
: 250ms (typ), 2.0s (max)
Page program time : 4.0ms/256 bytes (typ), 5.0ms/256 bytes (max)
Status functions
: Ready/busy information, protect information
Data retention period : 20 years
Package
: SOIC8 (150mil)
* This product is licensed from Silicon Storage Technology, Inc. (USA).
ORDERING INFORMATION
See detailed ordering and shipping information on page 23 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
February 2015 - Rev. 1
1
Publication Order Number :
LE25U40CMD/D







LE25U40CMD pdf, 数据表
LE25U40CMD
3. Status Registers
The status registers hold the operating and setting statuses inside the device, and this information can be read (status
register read) and the protect information can be rewritten (status register write). There are 8 bits in total, and "Table
4 Status registers" gives the significance of each bit.
Table 4. Status Registers
Bit Name
Bit0 RDY
Bit1 WEN
Bit2 BP0
Bit3 BP1
Bit4 BP2
Bit5 TB
Bit6
Bit7 SRWP
Logic
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Function
Ready
Erase/Program
Write disabled
Write enabled
Block protect information
Protecting area switch
Block protect
Upper side/Lower side switch
Reserved bits
Status register write enabled
Status register write disabled
Power-on Time Information
0
0
Nonvolatile information
Nonvolatile information
Nonvolatile information
Nonvolatile information
0
Nonvolatile information
3-1. Status register read
The contents of the status registers can be read using the status register read command. This command can be
executed even during the following operations.
Small sector erase, sector erase, chip erase
Page program
Status register write
"Figure 6 Status Register Read" shows the timing waveforms of status register read. Consisting only of the first bus
cycle, the status register command outputs the contents of the status registers synchronized to the falling edge of the
clock (SCK) with which the eighth bit of (05h) has been input. In terms of the output sequence, SRWP (bit 7) is the
first to be output, and each time one clock is input, all the other bits up to RDY (bit 0) are output in sequence,
synchronized to the falling clock edge. If the clock input is continued after RDY (bit 0) has been output, the data is
output by returning to the bit (SRWP) that was first output, after which the output is repeated for as long as the clock
input is continued. The data can be read by the status register read command at any time (even during a program or
erase cycle).
Figure 6. Status Register Read
CS
SCK
SI
SO
Mode 3
Mode 0
0 1 2 3 4 5 6 7 8 15 16 23
8CLK
MSB
05h
High Impedance
DATA DATA DATA
MSB MSB MSB
www.onsemi.com
8







LE25U40CMD equivalent, schematic
LE25U40CMD
LE25U40CMD incorporates a power-on reset function. The following conditions must be met in order to ensure
that the power reset circuit will operate stably.
No guarantees are given for data in the event of an instantaneous power failure occurring during the writing period.
Figure 19. Power-down Timing
VDD
VDD(Max)
VDD(Min)
tPD
0V vBOT
Power-on timing
Parameter
power-on to operation time
power-down time
power-down voltage
Symbol
tPU
tPD
tBOT
spec
min max
100
10
0.2
unit
µs
ms
V
14. Software Data Protection
The LE25U40CMD eliminates the possibility of unintentional operations by not recognizing commands under the
following conditions.
When a write command is input and the rising CS edge timing is not in a bus cycle (8 CLK units of SCK)
When the page program data is not in 1-byte increments
When the status register write command is input for 2 bus cycles or more
15. Decoupling Capacitor
A 0.1F ceramic capacitor must be provided to each device and connected between VDD and VSS in order to
ensure that the device will operate stably.
www.onsemi.com
16










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