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PDF ( 数据手册 , 数据表 ) 64F2646

零件编号 64F2646
描述 HD64F2646
制造商 Renesas
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64F2646 数据手册, 描述, 功能
Hitachi 16-Bit Single-Chip Microcomputer
H8S/2646 Series
H8S/2646
HD6432646
H8S/2645
HD6432645
H8S/2647
HD6432647
H8S/2648
HD6432648
H8S/2646R F-ZTAT™
HD64F2646R
H8S/2648R F-ZTAT™
HD64F2648R
Hardware Manual
ADE-602-207C
Rev. 4.0
9/20/02
Hitachi, Ltd.
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.







64F2646 pdf, 数据表
Section
9.13.2 Register
Configuration
15.2.3 Bit
Configuration
Register (BCR)
15.2.11 Interrupt
Register (IRR)
15.2.16 Unread
Message Status
Register (UMSR)
Page Description
283 Part F Data Register (PFDR)
Bit :
Initial value :
R/W
:
7
0
R/W
6
PF6DR
0
R/W
5
PF5DR
0
R/W
4
PF4DR
0
R/W
3
PF3DR
0
R/W
21 0
PF2DR
PF0DR
0 undefined 0
R/W R/W
2nd line changed as follows
PFDR is an 8-bit readable/writable register that stores output data for the port F
pins (PF6 to PF2, PF0).
6th line changed as follows
Bits 7 and 1 in PFDR are reserved, and only 0 may be written to it.
539 Figure of Detailed Description of Timing within 1 Bit, HCAN bit rate calculation,
BCR Setting Constraints, Table of Setting Range for TSEG1 and TSEG2 in
BCR
Moved to Bit Rate and Bit Timing Settings in section 15.3.2, Initialization after
Hardware Reset.
547 Bit 15Overload Frame Interrupt Flag: Status flag indicating that the HCAN
has transmitted an overload frame.
Bit 15: IRR7
Description
0 [Clearing condition]
Writing 1
(Initial value)
1 Overload frame transmission
[Setting conditions]
When overload frame is transmitted
555 Bit table amended and Note added
UMSR
Bit: 15 14 13 12 11 10
9
8
UMSR7 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0
Initial value: 0 0 0 0 0 0 0 0
R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Bit: 7 6 5 4 3 2 1 0
UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 UMSR8
Initial value: 0 0 0 0
R/W: R/(W)* R/(W)* R/(W)* R/(W)*
Note: * Only 1 can be written, to clear the flag.
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*







64F2646 equivalent, schematic









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