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PDF ( 数据手册 , 数据表 ) AP0202AT

零件编号 AP0202AT
描述 High-Dynamic Range (HDR) Image Signal Processor
制造商 ON Semiconductor
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AP0202AT 数据手册, 描述, 功能
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AP0202AT: Image Signal Processor (ISP)
Features
AP0202AT High-Dynamic Range (HDR) Image
Signal Processor (ISP)
AP0202AT Datasheet, Rev. 4
For the latest product datasheet, please visit www.onsemi.com
Features
• Up to 2.0 Mp (1920x1080) ON Semiconductor sensor
support
• 30 fps at 1080p, 45 fps at 1.2Mp, 60 fps at 720p
(Optimized for operation with HDR sensors)
• Color and gamma correction
• Auto exposure, auto white balance, 50/60 Hz auto
flicker detection and avoidance
• Adaptive Local Tone Mapping (ALTM)
• Two-wire serial programming interface (CCIS)
• Parallel output
• Configurable through low-cost SPI Flash and
EEPROM devices
• High-level host command interface
• Standalone operation supported
• Up to 7 GPIO
• Fail-safe IO
• Multi-Camera synchronization support
Applications
• Surround, rear and front view cameras
• Blind spot / side mirror replacement cameras
• Automotive viewing/processing fusion cameras
Table 1:
Key Performance Parameters
Parameter
Image sensor
interfaces
Input Data
FOrmat
Value
Parallel and HiSPi
Parallel: 12 bit SDR (linear) or
12 bit HDR companded.
Output interface
Output format
Maximum
resolution
Input clock range
Output pixel clock
maximum
Supply voltage
Operating temp.
(Ambient)
Power
consumption
HiSPI: 12 bit SDR (linear) or
12/14 bit HDR companded
Up to 24-bit parallel1
RGB888, RGB565, YUV422 8-/10-bit1
1920 x 1080 (2.0 Mp)
10 - 29 MHz
125 MHz2
VDDIO_S
VDDIO_H
VDD_REG
VDD
VDD_PLL
VDD_PHY
VDDIO_OTPM
–40°C to +105°C
1.8 or 2.8 V nominal
1.8 or 2.8 or 3.3 V
nominal
1.8 V nominal
1.2 V nominal
1.2 V nominal
2.8 V nominal
2.5 to 3.3 V nominal
250 mW
Notes: 1. Maximum frame rates depend on output interface and
data format configuration used.
2. Maximum pixel clock rates depend on IO voltage.
AP0202AT/D Rev. 4, 9/15 EN
1 ©Semiconductor Components Industries, LLC 2015,
‡This document contains information on a new product. Specifications and information herein are subject to change without notice.







AP0202AT pdf, 数据表
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AP0202AT: Image Signal Processor (ISP)
System Interfaces
System Interfaces
Figure 3 shows typical AP0202AT device connections.
All power supply rails must be decoupled from ground using capacitors as close as
possible to the package.
The AP0202AT signals to the sensor and host interfaces can be at different supply voltage
levels to optimize power consumption and maximize flexibility. Table 3 on page 11
provides the signal descriptions for the AP0202AT.
Figure 3: Typical Parallel Configuration - Legacy Mode
1.8V
Sensor IO ( R egulator
power
IP)
1 . 2 V ( R egulator OP)
P ower up C ore, P LL.
and DAC digital
PHY
power
OTPM
power
Host IO
power
VDDIO _S
M_S CLK
M_S DATA
EXTCLK_OUT
RESET_BAR_OUT
FV _IN
LV_IN
PIXCLK _IN
DIN [11:0]
OR HiSPiCN
HiSPiCP
HiSPi0N
HiSPi0P
HiSPi1N
HiSPi1P
TRIGGER_OUT/
GPIO_0
GND
VDDIO _H
S CLK
S DATA
S ADDR
STANDBY
EXTCLK
XTAL
RESET_BAR
FV_OUT
LV_OUT
PIXCLK_OUT
D OUT[23:0]
S P I_CS_BAR
SPI_CLK
SPI_SDO
SPI_SDI
GPIO_[6:1]
RESERVED_[1:0]
EXT_REG
TEST5
VDDIO_S6 VDD_REG4 LDO_OP4
VDDIO_OTPM VDDIO_H
Notes: 1. This typical configuration shows only one scenario out of multiple possible variations for this
device.
AP0202AT/D Rev. 4, Pub. 9/15 EN
8 ©Semiconductor Components Industries, LLC, 2015.







AP0202AT equivalent, schematic
Advance
AP0202AT: Image Signal Processor (ISP)
Power-Up Sequence
Table 7:
Output States (Continued)
Hardware States
Firmware States
Name
HiSPiCN
HiSPiCP
HiSPi0N
HiSPi0P
HiSPi1N
HiSPi1P
FV_OUT, LV_OUT,
PIXCLK_OUT
GPIO[6:1]
TRIGGER_OUT
TEST
Default
Reset State State
Disabled Disabled
High-
impedance
High-
impedance
High-
impedance
n/a
Varied
Input, then
high-
impedance
High-
impedance
n/a
Hard
Standby
Soft
Standby
Streaming
Dependent
on
interface
used
Dependent
on interface
used
Dependent
on interface
used
Driven if
used
Driven if
used
Driven if
used
Driven if
used
Driven if
used
Driven if
used
Driven if
used
(negated)
Driven if
used
(negated)
Driven if
used
(negated)
Idle Notes
Dependent Input. Will be disabled and
on interface can be left floating
used
Driven if
used
Driven if
used
Output. Default state
dependent on configuration
Input/Output.
Driven if
used
(negated)
Input. Must always be driven
to a valid logic level.
Hard Reset
The AP0202AT enters the reset state when the external RESET_BAR signal is asserted
LOW, as shown in Figure 6. All the output signals will be in a High-Z state.
Figure 6: Hard Reset Operation
EXTCLK
RESET_BAR
t1
t2 t3
t4
SDATA
All Outputs Data Active
State
Reset
Internal Initialization Time
Data Active
Enter streaming state
AP0202AT/D Rev. 4, Pub. 9/15 EN
16
©Semiconductor Components Industries, LLC, 2015.










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