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零件编号 | MTV16N50E | ||
描述 | Power Field Effect Transistor | ||
制造商 | ON Semiconductor | ||
LOGO | |||
1 Page
MTV16N50E
Advance Information
TMOS E−FET.™
Power Field Effect
Transistor
D3PAK for Surface Mount
N−Channel Enhancement−Mode Silicon
Gate
This high voltage MOSFET uses an advanced termination scheme to
provide enhanced voltage−blocking capability without degrading
performance over time. In addition, this advanced TMOS E−FET is
designed to withstand high energy in the avalanche and commutation
modes. The new energy efficient design also offers a drain−to−source
diode with a fast recovery time. Designed for high speed switching
applications in power supplies, converters, PWM motor controls, these
devices are particularly well suited for bridge circuits where diode
speed and commutating safe operating areas are critical and offer
additional safety margin against unexpected voltage transients.
• Robust High Voltage Termination
• Avalanche Energy Specified
• Source−to−Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
http://onsemi.com
TMOS POWER FET
16 AMPERES, 500 VOLTS
RDS(on) = 0.40 W
D3PAK Surface Mount
CASE 433−01
Style 2
D
N−Channel
®G
S
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Drain−to−Source Voltage
Drain−to−Gate Voltage (RGS = 1.0 MΩ)
Gate−to−Source Voltage — Continuous
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 μs)
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C (1)
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche Energy — Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 10 Vdc, Peak IL = 16 Apk, L = 6.7 mH, RG = 25 Ω )
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 1
1
Symbol
VDSS
VDGR
VGS
ID
ID
IDM
PD
TJ, Tstg
EAS
RθJC
RθJA
RθJA
TL
Value
500
500
±20
16
9.0
60
180
1.4
2.0
−55 to 150
860
0.7
62.5
35
260
Unit
Vdc
Vdc
Vdc
Adc
Apk
Watts
W/°C
Watts
°C
mJ
°C/W
°C
Publication Order Number:
MTV16N50E/D
MTV16N50E
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads.
Solder stencils are used to screen the optimum amount.
These stencils are typically 0.008 inches thick and may be
made of brass or stainless steel. For packages such as the
SC−59, SC−70/SOT−323, SOD−123, SOT−23, SOT−143,
SOT−223, SO−8, SO−14, SO−16, and SMB/SMC diode
packages, the stencil opening should be the same as the pad
size or a 1:1 registration. This is not the case with the DPAK
and D2PAK packages. If one uses a 1:1 opening to screen
solder onto the drain pad, misalignment and/or
“tombstoning” may occur due to an excess of solder. For
these two packages, the opening in the stencil for the paste
should be approximately 50% of the tab area. The opening
for the leads is still a 1:1 registration. Figure 16 shows a
typical stencil for the DPAK and D2PAK packages. The
pattern of the opening in the stencil for the drain pad is not
critical as long as it allows approximately 50% of the pad to
be covered with paste.
ÇÇÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ
ÇÇÇÇSOLDER PASTE
OPENINGS
STENCIL
Figure 16. Typical Stencil for DPAK and
D2PAK Packages
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied during
cooling.
* Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
* Due to shadowing and the inability to set the wave height
to incorporate other surface mount components, the D2PAK
is not recommended for wave soldering.
http://onsemi.com
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下载 | [ MTV16N50E.PDF 数据手册 ] |
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