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PDF ( 数据手册 , 数据表 ) MTB15N06V

零件编号 MTB15N06V
描述 Power Field Effect Transistor
制造商 ON Semiconductor
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MTB15N06V 数据手册, 描述, 功能
MTB15N06V
Designer’sData Sheet
TMOS V
Power Field Effect
Transistor
D2PAK for Surface Mount
NChannel EnhancementMode Silicon
Gate
TMOS V is a new technology designed to achieve an onresistance
area product about onehalf that of standard MOSFETs. This new
technology more than doubles the present cell density of our 50 and 60
volt TMOS devices. Just as with our TMOS EFET designs, TMOS V
is designed to withstand high energy in the avalanche and
commutation modes. Designed for low voltage, high speed switching
applications in power supplies, converters and power motor controls,
these devices are particularly well suited for bridge circuits where
diode speed and commutating safe operating areas are critical and
offer additional safety margin against unexpected voltage transients.
New Features of TMOS V
Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors
Features Common to TMOS V and TMOS EFETs
Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and TMOS EFET
Surface Mount Package Available in 16 mm 13inch/2500 Unit Tape
& Reel, Add T4 Suffix to Part Number
http://onsemi.com
TMOS POWER FET
15 AMPERES, 60 VOLTS
RDS(on) = 0.12 W
D2PAK
CASE 418B02,
Style 2
D
G
TM
S
© Semiconductor Components Industries, LLC, 2006
August, 2006 Rev. 3
1
Publication Order Number:
MTB15N06V/D







MTB15N06V pdf, 数据表
MTB15N06V
INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.33
8.38
0.42
10.66
0.63
17.02
0.08
2.032
0.04
1.016
0.24
6.096
0.12
3.05
inches
mm
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
The power dissipation for a surface mount device is a
function of the drain pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a surface
mount device is determined by TJ(max), the maximum rated
junction temperature of the die, RθJA, the thermal resistance
from the device junction to ambient, and the operating
temperature, TA. Using the values provided on the data
sheet, PD can be calculated as follows:
PD =
TJ(max) TA
RθJA
almost double the power dissipation with this method, one
will be giving up area on the printed circuit board which can
defeat the purpose of using surface mount technology. For
example, a graph of RθJA versus drain pad area is shown in
Figure 16.
70
Board Material = 0.0625
G−10/FR−4, 2 oz Copper TA = 25°C
60
2.5 Watts
50
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device. For a D2PAK
device, PD is calculated as follows.
PD =
175°C 25°C = 3.0 Watts
50°C/W
The 50°C/W for the D2PAK package assumes the use of
the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 3.0 Watts. There are
other alternatives to achieving higher power dissipation from
the surface mount packages. One is to increase the area of
the drain pad. By increasing the area of the drain pad, the
power dissipation can be increased. Although one can
3.5 Watts
40
5 Watts
30
20
0 2 4 6 8 10 12 14 16
A, AREA (SQUARE INCHES)
Figure 16. Thermal Resistance versus Drain Pad
Area for the D2PAK Package (Typical)
Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
http://onsemi.com
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