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PDF ( 数据手册 , 数据表 ) IZ1325

零件编号 IZ1325
描述 High-precision Real Time Clock circuit
制造商 Integral
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IZ1325 数据手册, 描述, 功能
IZ1325
High-precision Real Time Clock circuit
with thermal compensation and built-in quartz resonator
(Functional analogue of RX8025SA by Company « Epson Toyocom »)
The IZ1325 high-precision real-time clock circuit with thermal compensation and built-in quartz
resonator, provides high accuracy counting the current time of the, generation of 6 system inter-
ruptions and two independent event signals. The device provides both 24/12-hour operation
modes and contains the built-in supply control circuit, frequency adjustment circuit for high ac-
curacy of the system generator. The IZ1325 support data and command exchange by means of
standard 2-wire interface (I2C-bus).
The IC is applied in the wide range of the industrial and household equipment and appli-
ances, where it is required to counting and processing of the system current time data.
Main functions:
seconds, minites hours, weekday, date, month and year time counting;
two operational modes12/24-hours;
data and command exchange via 2-wire I2C-bus serial interface;
6 system interrupts generation;
2 independent alarms: day, hours, minutes and hours, minutes;
supply voltage and system generator frequency monitoring.
Main features:
Supply voltage, UDD, 1,7 … 5,5 V
Oscilator operating supply voltage UCLK, 1,15 … 5,5 V
Operating temperature range -40 to +85 °С
Table 1 – Contact pad description
Contact
pad num-
ber
01
02
03
04
05
06
07
08
09
10
11
Symbol
GND
INTA
X1
X2
FOE
VDD
TEST
FOUT
SCL
SDA
INTB
Description
Ground
Interrupt output A
Quartz resonator input
Quartz resonator output
Control input
Power supply
Test terminal
32.768 kHz clock output
I2C bus clock input
I2C bus input-output
Interrupt output B
Ver.1.0/02.11.2010
1 IZ1325-TSe
549888
www.bms.by







IZ1325 pdf, 数据表
Input /Output
SDA
START
RESTART
IZ1325
STOP
Input
SCL
Fig. 5 –START and STOP conditions
Data transfer and reception acknowledge
Each data transfer starts with START condition and ceases with STOP condition. The num-
ber of data bytes, transferred between the START and STOP conditions, is not limited and is
specified by the «master» device. (but, the transfer time should not exceed 0,5s) Data is transferred
byte by byte, and each byte reception is confirmed by the ninth (acknowledge) bit.
Data line state corresponds to the valid data, if after the condition START the data line remain
stable during the HIGH period of the clock pulse. Changes of the data line have to be performed
during the LOW period of the clock pulse. One data bit is transferred during each clock pulse.
Data
valid
Data changing
can be proceed
Input / Output
SDA
Input
SCL
Fig. 6 –Data transfer
Ver.1.0/02.11.2010
8 IZ1325-TSe
549888
www.bms.by














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