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PDF ( 数据手册 , 数据表 ) R5F51305ADNE

零件编号 R5F51305ADNE
描述 32-bit RX MCUs
制造商 Renesas
LOGO Renesas LOGO 


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R5F51305ADNE 数据手册, 描述, 功能
Datasheet
RX130 Group
Renesas MCUs
32-MHz, 32-bit RX MCUs, 50 DMIPS, up to 128-KB flash memory,
R01DS0273EJ0100
Rev.1.00
Oct 30, 2015
up to 36 pins capacitive touch sensing unit, up to 6 comms channels, 12-bit A/D, D/A, RTC,
IEC60730 compliance, 1.8-V to 5.5-V single supply
Features
32-bit RX CPU core
Max. operating frequency: 32 MHz
Capable of 50 DMIPS in operation at 32 MHz
Accumulator handles 64-bit results (for a single instruction) from
32-bit × 32-bit operations
Multiplication and division unit handles 32-bit × 32-bit operations
(multiplication instructions take one CPU clock cycle)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions, ultra-compact code
On-chip debugging circuit
Low power design and architecture
Operation from a single 1.8-V to 5.5-V supply
Three low power consumption modes
Low power timer (LPT) that operates during the software standby state
Supply current
High-speed operating mode: 96 A/MHz
Supply current in software standby mode: 0.37 A
Recovery time from software standby mode: 4.8 s
On-chip flash memory for code, no wait states
Operation at 32 MHz, read cycle of 31.25 ns
No wait states for reading at full CPU speed
Programmable at 1.8 V
For instructions and operands
On-chip data flash memory
8 Kbytes (1,000,000 program/erase cycles (typ.))
BGO (Background Operation)
On-chip SRAM, no wait states
10- to 16-Kbyte size capacities
DTC
Four transfer modes
Transfer can be set for each interrupt source.
ELC
Module operation can be initiated by event signals without using
interrupts.
Linked operation between modules is possible while the CPU is sleeping.
Reset and supply management
Eight types of reset, including the power-on reset (POR)
Low voltage detection (LVD) with voltage settings
Clock functions
External clock input frequency: Up to 20 MHz
Main clock oscillator frequency: 1 to 20 MHz
Sub clock oscillator frequency: 32.768 kHz
PLL circuit input: 4 MHz to 8 MHz
Low-speed on-chip oscillator: 4 MHz
High-speed on-chip oscillator: 32 MHz ± 1 %
IWDT-dedicated on-chip oscillator: 15 kHz
Generate a 32.768 kHz clock for the real-time clock
On-chip clock frequency accuracy measurement circuit (CAC)
Realtime clock
Adjustment functions (30 seconds, leap year, and error)
Calendar count mode or binary count mode selectable
Independent watchdog timer
15-kHz on-chip oscillator produces a dedicated clock signal to drive
IWDT operation.
Useful functions for IEC60730 compliance
Self-diagnostic and disconnection-detection assistance functions for
the A/D converter, clock frequency accuracy measurement circuit,
independent watchdog timer, RAM test assistance functions using the
DOC, etc.
PLQP0080KB-B 12 × 12mm, 0.5mm pitch
PLQP0064GA-A 14 × 14mm, 0.8mm pitch
PLQP0064KB-C 10 × 10mm, 0.5mm pitch
PLQP0048KB-B 7 × 7mm, 0.5mm pitch
PWQN0048KB-A 7 × 7mm, 0.5mm pitch
MPC
Input/output functions selectable from multiple pins
Up to 6 communication functions
SCI with many useful functions (up to 4 channels)
Asynchronous mode (Fine adjustable baud rate: 0 to 255/255), clock
synchronous mode, smart card interface mode
I2C bus interface: Transfer at up to 400 kbps, capable of SMBus
operation (one channel)
RSPI (one channel): Transfer at up to 16 Mbps
Up to 12 extended-function timersMPC
16-bit MTU: input capture, output compare, complementary PWM
output, phase counting mode (six channels)
8-bit TMR (four channels)
16-bit compare-match timers (two channels)
12-bit A/D converter
Capable of conversion within 1.4 μs
17 channels
Sampling time can be set for each channel
Conversion results compare features
Self-diagnostic function and analog input disconnection detection
assistance function
Double trigger (data duplication) function for motor control
D/A converter
Two channels
Capacitive touch sensing unit
Self-capacitance method: A single pin configures a single key,
supporting up to 36 keys
Mutual capacitance method: Matrix configuration with 36pins, supporting
up to 324 keys
Comparator B
Two channels
General I/O ports
5-V tolerant, open drain, input pull-up, switching of driving capacity
Temperature sensor
Unique ID
32-byte ID code for the MCU
Operating temperature range
 40 to +85C
 40 to +105C
Applications
General industrial and consumer equipment
R01DS0273EJ0100 Rev.1.00
Oct 30, 2015
Page 1 of 116







R5F51305ADNE pdf, 数据表
RX130 Group
1.3 Block Diagram
Figure 1.2 shows a block diagram.
1. Overview
ROM
RAM
RX CPU
Clock
generation
circuit
ICUb
DTCa
E2 DataFlash
IWDTa
ELC
CRC
SCIg × 3 channels
SCIh × 1 channel
RSPIa × 1 channel
RIICa × 1 channel
MTU2a × 6 channels
POE2a
TMR × 2 channels (unit 0)
TMR × 2 channels (unit 1)
CMT × 2 channels (unit 0)
RTCc
12-bit A/D converter × 17 channels
Temperature sensor
8-bit D/A converter × 2 channels
DOC
Comparator B
CAC
CTSUa
LPT
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port A
Port B
Port C
Port D
Port E
Port H
Port J
ICUb:
Interrupt controller
DTCa:
Data transfer controller
IWDTa: Independent watchdog timer
ELC:
Event link controller
CRC:
CRC (cyclic redundancy check) calculator
SCIg/SCIh: Serial communications interface
RSPIa: Serial peripheral interface
RIICa:
I2C bus interface
MTU2a: Multi-function timer pulse unit 2
Figure 1.2
Block Diagram
POE2a:
CMT:
RTCc:
DOC:
CAC:
CTSUa:
TMR:
LPT:
Port output enable 2
Compare match timer
Realtime clock
Data operation circuit
Clock frequency accuracy measurement circuit
Capacitive touch sensing unit
8-bit timer
Low power timer
R01DS0273EJ0100 Rev.1.00
Oct 30, 2015
Page 8 of 116







R5F51305ADNE equivalent, schematic
RX130 Group
1. Overview
Table 1.5
List of Pins and Pin Functions (80-Pin LFQFP) (2/2)
Pin Power Supply, Clock,
Timers
No. System Control
I/O Port (MTU, TMR, POE)
50 VSS
51 PA6 MTIC5V/MTCLKB/TMCI3/
POE2#
52 PA5
53 PA4 MTIC5U/MTCLKA/TMRI0
54 PA3 MTIOC0D/MTCLKD
55 PA2
56 PA1 MTIOC0B/MTCLKC
57 PA0 MTIOC4A
58 PE5 MTIOC4C/MTIOC2B
59 PE4 MTIOC4D/MTIOC1A
Communications
(SCIg, SCIh, RSPI, RIIC)
CTS5#/RTS5#/SS5#/MOSIA
RSPCKA
TXD5/SMOSI5/SSDA5/SSLA0
RXD5/SMISO5/SSCL5
RXD5/SMISO5/SSCL5/SSLA3
SCK5/SSLA2
SSLA1
60
PE3 MTIOC4B/POE8#
CTS12#/RTS12#/SS12#
61
PE2 MTIOC4A
RXD12/RXDX12/SMISO12/SSCL12
62
PE1 MTIOC4C
TXD12/TXDX12/SIOX12/SMOSI12/
SSDA12
63 PE0
SCK12
64
PD2 MTIOC4D
SCK6
65
PD1 MTIOC4B
RXD6/SMISO6/SSCL6
66 PD0
TXD6/SMOSI6/SSDA6
67 P47*2
68 P46*2
69 P45*2
70 P44*2
71 P43*2
72 P42*2
73 P41*2
74 VREFL0
PJ7*2
75 P40*2
76 VREFH0
PJ6*2
77 AVCC0
78 P07*2
79 AVSS0
80 P05*2
Note 1. PC0 and PC1 are valid only when the port switching function is selected.
Note 2. The power source of the I/O buffer for these pins is AVCC0.
Touch
sensing Others
TS26
TS27
TS28
TS29
TS30
TS31
TS32
TS33
TS34
TS35
IRQ5/CVREFB1
IRQ6/CMPB1
CACREF
IRQ5/AN021/CMPOB0
AN020/CMPA2/
CLKOUT
AN019/CLKOUT
IRQ7/AN018/CVREFB0
AN017/CMPB0
AN016
IRQ2/AN026
IRQ1/AN025
IRQ0/AN024
AN007
AN006
AN005
AN004
AN003
AN002
AN001
AN000
ADTRG0#
DA1
R01DS0273EJ0100 Rev.1.00
Oct 30, 2015
Page 16 of 116










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