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零件编号 | R5F51138AGFM | ||
描述 | 32-Bit MCU | ||
制造商 | Renesas | ||
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1 Page
Cover
RX113 Group
32
User’s Manual: Hardware
RENESAS 32-Bit MCU
RX Family / RX100 Series
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
www.renesas.com
Rev.1.02 Dec 2014
3. List of Abbreviations and Acronyms
Abbreviation
ACIA
bps
CRC
DMA
DMAC
GSM
Hi-Z
IEBus
I/O
IrDA
LSB
MSB
NC
PLL
PWM
SIM
UART
VCO
Full Form
Asynchronous Communications Interface Adapter
bits per second
Cyclic Redundancy Check
Direct Memory Access
Direct Memory Access Controller
Global System for Mobile Communications
High Impedance
Inter Equipment Bus
Input/Output
Infrared Data Association
Least Significant Bit
Most Significant Bit
Non-Connect
Phase Locked Loop
Pulse Width Modulation
Subscriber Identity Module
Universal Asynchronous Receiver/Transmitter
Voltage Controlled Oscillator
All trademarks and registered trademarks are the property of their respective owners.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United
States and Japan.
Caution: This product uses SuperFlash technology licensed from Silicon Storage Technology, Inc.
15.4.1 Type of Bus Error ..................................................................................................................... 290
15.4.1.1 Illegal Address Access .................................................................................................... 290
15.4.1.2 Timeout ............................................................................................................................ 290
15.4.2 Operations When a Bus Error Occurs ...................................................................................... 290
15.4.3 Conditions Leading to Bus Errors ............................................................................................ 291
16. Data Transfer Controller (DTCa) .................................................................................................. 292
16.1 Overview ........................................................................................................................................... 292
16.2 Register Descriptions ......................................................................................................................... 294
16.2.1 DTC Mode Register A (MRA) ................................................................................................. 294
16.2.2 DTC Mode Register B (MRB) ................................................................................................. 295
16.2.3 DTC Transfer Source Register (SAR) ...................................................................................... 296
16.2.4 DTC Transfer Destination Register (DAR) .............................................................................. 296
16.2.5 DTC Transfer Count Register A (CRA) ................................................................................... 297
16.2.6 DTC Transfer Count Register B (CRB) ................................................................................... 298
16.2.7 DTC Control Register (DTCCR) .............................................................................................. 298
16.2.8 DTC Vector Base Register (DTCVBR) ................................................................................... 299
16.2.9 DTC Address Mode Register (DTCADMOD) ......................................................................... 299
16.2.10 DTC Module Start Register (DTCST) ...................................................................................... 300
16.2.11 DTC Status Register (DTCSTS) ............................................................................................... 301
16.3 Activation Sources ............................................................................................................................. 302
16.3.1 Allocating Transfer Information and DTC Vector Table ......................................................... 302
16.4 Operation ........................................................................................................................................... 304
16.4.1 Transfer Information Read Skip Function ................................................................................ 306
16.4.2 Transfer Information Write-Back Skip Function ..................................................................... 307
16.4.3 Normal Transfer Mode ............................................................................................................. 308
16.4.4 Repeat Transfer Mode .............................................................................................................. 309
16.4.5 Block Transfer Mode ............................................................................................................... 310
16.4.6 Chain Transfer .......................................................................................................................... 311
16.4.7 Operation Timing ..................................................................................................................... 312
16.4.8 Execution Cycles of the DTC ................................................................................................... 315
16.4.9 DTC Bus Mastership Release Timing ...................................................................................... 315
16.5 DTC Setting Procedure ...................................................................................................................... 316
16.6 Examples of DTC Usage ................................................................................................................... 317
16.6.1 Normal Transfer ....................................................................................................................... 317
16.6.2 Chain Transfer When the Counter = 0 ..................................................................................... 318
16.7 Interrupt Source ................................................................................................................................. 319
16.8 Event Link ......................................................................................................................................... 319
16.9 Low Power Consumption Function ................................................................................................... 320
16.10 Usage Notes ....................................................................................................................................... 321
16.10.1 Transfer Information Start Address .......................................................................................... 321
16.10.2 Allocating Transfer Information ............................................................................................... 321
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页数 | 30 页 | ||
下载 | [ R5F51138AGFM.PDF 数据手册 ] |
零件编号 | 描述 | 制造商 |
R5F51138AGFM | 32-Bit MCU | Renesas |
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