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PDF ( 数据手册 , 数据表 ) PL602-37

零件编号 PL602-37
描述 750kHz - 800MHz Low Phase Noise Multiplier XO
制造商 Micrel
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PL602-37 数据手册, 描述, 功能
PL602-35/-37/-38/-39
750kHz 800MHz Low Phase Noise Multiplier XO
Universal Low Phase Noise IC’s
FE AT UR E S
PIN CONFIGURATION
Selectable 750kHz to 800MHz range.
Low phase noise output
-127dBc/Hz for 155.52MHz @ 10kHz offset
-115dBc/Hz for 622.08MHz @ 10kHz offset
LVCMOS (PL602-37), LVPECL (PL602-35 and
PL602-38) or LVDS (PL602-39) output.
12MHz to 25MHz crystal input.
No external crystal load capacitors required.
Output Enable selector.
Selectable /16 to x32 frequency divider/multiplier.
3.3V operation.
Available in 16-Pin TSSOP or 16-pin 3x3mm QFN
GREEN/RoHS compliant packages.
(Top View)
VDD
XIN
XOUT
SEL3^
SEL2^
OE
GND
GND
1
1
6
2
1
5
3
1
4
4
1
3
5
1
2
6
1
1
7
1
0
89
TSSOP-16L
SEL0^
SEL1^
GND
CLKC
VDD
CLKT
GND
GND
DESCRIPTION
The PL602-35 (LVPECL with inverted OE), PL602-37
(LVCMOS), PL602-38 (LVPECL), and PL602-39
(LVDS) are high performance and low phase noise XO
IC chips. They provide phase noise performance as
low as 127dBc at 10kHz offset (at 155MHz), by multi-
plying the input crystal frequency up to 32x. The very
low jitter makes them ideal for a wide range of applica-
tions, including SONET/SDH and FEC. They accept
fundamental parallel resonant mode crystals from
12MHz to 25MHz.
XOUT
SEL3^
SEL2^
OE
12
13
11 10
9
8
14
PL602-3x
7
15 6
16 5
123 4
GND
CLKC
VDD
CLKT
BLOCK DIAGRAM
SEL[3:0]
XIN
XOUT
Oscillator
Amplifier
w/
integrated
load cap.
PLL
(Phase
Locked
Loop)
PLL by-pass
OE
CLKC
QFN-16L
^: Internal pull-up
*: On QFN package, PL602-35/-38 do not have SEL0 available: Pin 10
is VDD, pin 11 is GND. However, PL602-37/-39 have SEL0 (pin 10),
and pin11 is VDD. See pin assignment table for details.
Note: On QFN package there is a large center pad for thermal relief.
This pad needs to be connected to GND.
CLKT OUTPUT ENABLE LOGICAL LEVELS
Part #
OE
State
PL602-3x
PL602-38
PL602-35
PL602-37
PL602-39
0 (Default)
1
0
1 (Default)
Output enabled
Tri-state
Tri-state
Output enabled
OE input: Logical states defined by LVPECL levels for PL602-38
Logical states defined by LVCMOS levels for PL602-37/-39
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 03/07/2012 Page 1







PL602-37 pdf, 数据表
PL602-35/-37/-38/-39
750kHz 800MHz Low Phase Noise Multiplier XO
Universal Low Phase Noise IC’s
PACKAGE INFORMATION (GREEN PACKAGE COMPLIANT)
TSSOP-16L
Symbol
A
A1
b
C
D
E
H
L
e
Dimension in MM
Min.
Max.
- 1.20
0.05
0.15
0.19
0.30
0.09
0.20
4.90
5.10
4.30
4.50
6.20
6.60
0.45
0.75
0.65 BSC
EH
D
A1
eB
C
A
L
QFN-16L
Symbol
A
A1
A3
b
D
E
D1
E1
L
e
Dimension (mm)
Min Nom Max
0.70 0.75 0.80
0.00 - 0.05
0.20
0.20 0.25 0.30
2.95 3.00 3.05
2.95 3.00 3.05
1.65 1.70 1.75
1.65 1.70 1.75
0.250 0.300 0.350
0.50BSC
e
L
D1
DDD
b
A
SEATING
PLANE
Pin1 Dot
A3
A1
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 03/07/2012 Page 8














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