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PDF ( 数据手册 , 数据表 ) IZ7012

零件编号 IZ7012
描述 8-BIT MICROCONTROLLER
制造商 Integral
LOGO Integral LOGO 


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IZ7012 数据手册, 描述, 功能
IZ7012
8-BIT CONTROLLER WITH FLASH MEMORY OF PROGRAMS
The microcircuit IZ7012 – 8-bit controller with the FLASH – memory of programs (ROM test-
ing coding with the watch functions, stopwatch with the possibility of the intermediate values fixa-
tion and writing of thirty results into memory).
The microcircuit is intended for receipt, processing and indication of data on the liquid crystal
indicator The microcircuit is applicable in the electronic household appliance devices (counters,
electronic watches, electronic thermometers, pedometers).
Main characteristics:
ROM capacity, QROM, bit………………………………3072х16;
PROM capacity, QROM1, bit……………………………1024х16;
RAM capacity, QRAM, byte…………………..………....128;
Number of bits of ALU, bits……………………………8;
Sources of interruptions…………………………….….from 8 inputs,
From event counter at input IN8,
from three timers;
Maximum number of controlled……………..……….136 (34 LCD control drivers
LCD segments…………………………………….......at multiplex levels 1/2,1/3,1/4);
RISC-system of commands…………………………30 types of commands;
Stack……………………………………………………7 levels;
Permissible value of potential
of static electricity, V………………..…………..…....1500
(for pins IN1-IN8, OSCI, OSCO)……………..…..….(1000)
Operating temperature range …………………..…- 40 … +85 °С.
Ver.01/16.04.2009
1







IZ7012 pdf, 数据表
IZ7012
Operation description
Reprogrammed ROM
Reprogrammed ROM is used for storage of commands or data and contains 1024 com-
mands (16-bit instructions) at addresses from 0xС00 to 0xFFF. Area of the reprogrammed ROM
within the address range from 0xС00 to 0xС01 (2 commands) is reserved for the 26-bit control total
of the reprogrammed ROM codes and the six bit sign of the reprogrammed ROM initial testing and
granting permission for writing. The reprogrammed ROM area within the address range from
0xС02 to 0xС0A (9 commands) is reserved for the transfer commands for the initial subprogram
addresses of the interruptions processing, located in the reprogrammed ROM area. Transfer to
these addresses is performed after execution of the interruption processing programs, located in
ROM, transfer to which is executed by the hardware means.
Table 6 – Initial addresses of interruption processing subprograms
Address
Interruption Source
Remarks
0xС02
Power supply switch
-
0xС03
0xС04
0xС05
0xС06
0xС07
0xС08
Timers 1, 2 and 3 simultaneously
Timers 2 and 3 simultaneously
Timers 1 and 3 simultaneously
Timers 1 and 2 simuiltaneously
Timer 3
Timer 2
Simultaneously with the tim-
ers it is possible to initiate in-
terruption from the input port,
which is required to take into
consideration in the interrup-
tion servicing programs
0xС09
Timer 1
0xС0A
Input port
-
Programming of the reprogrammed ROM is performed under control of the program from
ROM.
ROM
ROM contains 3072 commands (16-bit instructions) at the addresses from 0x000 to 0xBFF.
The ROM area within the range from 0x000 to 0x0FF (256 commands) is reserved for the interrup-
tion servicing and controller testing programs. The ROM areas with the addresses 0x7e, 0x7f and
the addresses from 0x7FE to 0x801 (4 commands) are reserved for the control ROM total and the
stack registers test, checked during the controller testing.
Table 7 – Initial addresses of interruption processing subprograms
(in the order of the priority diminishing)
Address
Interruption Source
Remarks
0x000
Power supply switch on
-
0x08F
Timers 1, 2 and 3 simultaneously
Simultaneously with the
0x09F
0x0AF
0x0CF
0x0BF
0x0DF
0x0EF
Timers 2 and 3 simultaneously
Timers 1 and 3 simultaneously
Timers 1 and 2 simultaneously
Timer 3
Timer 2
Timer 1
timers it is possible to initiate
interruption from the input
port, which is required to be
taken into consideration in the
interruption servicing pro-
grams
0x0FF
Input port
-
ROM is for location of the interruption processing and controller testing programs, including
the reprogrammed ROM block testing, the reprogrammed ROM erasure and writing control pro-
grams, library of the applied subprograms.
Ver.00/16.04.2009
8







IZ7012 equivalent, schematic
IZ7012
LCD Driver Memory
At RFС0_1=0 and RFС0_0=0 the multiplex level is selected to be 1/4.
At RFС0_1=0 and RFС0_0=1 the multiplex level is selected to be 1/3.
At RFС0_1=1 the multiplex level is selected to be 1/2.
Table 11 – Purpose of LCD Driver Memory Bits
Configuration of LCD Driver Memory at Multiplex Level 1/4
Register
Bank Number Address Bit_7
in Bank
Bit_6
Bit_5
Bit_4
Bit_3
Bit_2
Bit_1
Bit_0 COM
0 0x7E8 SEG04 SEG06 SEG08 SEG10 SEG12 SEG14 SEG16 SEG18 COM1
1 0x7E9 SEG04 SEG06 SEG08 SEG10 SEG12 SEG14 SEG16 SEG18 COM2
2 0x7EA SEG04 SEG06 SEG08 SEG10 SEG12 SEG14 SEG16 SEG18 COM3
FD 3 0x7EB SEG04 SEG06 SEG08 SEG10 SEG12 SEG14 SEG16 SEG18 COM4
4 0x7EC SEG03 SEG05 SEG07 SEG09 SEG11 SEG13 SEG15 SEG17 COM1
5 0x7ED SEG03 SEG05 SEG07 SEG09 SEG11 SEG13 SEG15 SEG17 COM2
6 0x7EE SEG03 SEG05 SEG07 SEG09 SEG11 SEG13 SEG15 SEG17 COM3
7 0x7EF SEG03 SEG05 SEG07 SEG09 SEG11 SEG13 SEG15 SEG17 COM4
0 0x7E0 SEG33 SEG31 SEG29 SEG27 SEG25 SEG23 SEG21 SEG19 COM1
1 0x7E1 SEG33 SEG31 SEG29 SEG27 SEG25 SEG23 SEG21 SEG19 COM2
2 0x7E2 SEG33 SEG31 SEG29 SEG27 SEG25 SEG23 SEG21 SEG19 COM3
FE 3 0x7E3 SEG33 SEG31 SEG29 SEG27 SEG25 SEG23 SEG21 SEG19 COM4
4 0x7E4 SEG34 SEG32 SEG30 SEG28 SEG26 SEG24 SEG22 SEG20 COM1
5 0x7E5 SEG34 SEG32 SEG30 SEG28 SEG26 SEG24 SEG22 SEG20 COM2
6 0x7E6 SEG34 SEG32 SEG30 SEG28 SEG26 SEG24 SEG22 SEG20 COM3
7 0x7E7 SEG34 SEG32 SEG30 SEG28 SEG26 SEG24 SEG22 SEG20 COM4
FB
4
0x7DC
SEG02
COM1
SEG02
COM2
SEG02
COM3
SEG02
COM4
SEG01
COM1
SEG01
COM2
SEG01
COM3
SEG01
COM4
_
Ver.00/16.04.2009
16










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