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PDF ( 数据手册 , 数据表 ) SH1106

零件编号 SH1106
描述 132 X 64 Dot Matrix OLED/PLED Segment/Common Driver
制造商 SINO WEALTH
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SH1106 数据手册, 描述, 功能
SH1106
Preliminary
132 X 64 Dot Matrix OLED/PLED
Segment/Common Driver with Controller
Features
„ Support maximum 132 X 64 dot matrix panel
„ Embedded 132 X 64 bits SRAM
„ Operating voltage:
- Logic voltage supply: VDD1 = 1.65V - 3.5V
- DC-DC voltage supply: VDD2 = 3.0V – 4.2V
- OLED Operating voltage supply:
External VPP supply = 6.4V - 13.0V
Internal VPP generator = 6.4V - 9.0V
„ Maximum segment output current: 200μA
„ Maximum common sink current: 27mA
„ 8-bit 6800-series parallel interface, 8-bit 8080-series
parallel interface, 3-wire & 4-wire serial peripheral
interface, 400KHz fast I2C bus interface
„ Programmable frame frequency and multiplexing ratio
„ Row re-mapping and column re-mapping (ADC)
„ Vertical scrolling
„ On-chip oscillator
„ Programmable Internal charge pump circuit output
„ 256-step contrast control on monochrome passive OLED
panel
„ Low power consumption
- Sleep mode: <5μA
- VDD1=0VVDD2=3.0V – 4.2V: <5μA
- VDD1,2=0VVPP=3.0V – 4.2V: <5μA
„ Wide range of operating temperatures: -40 to +85°C
„ Available in COG form, thickness: 300μm
General Description
SH1106 is a single-chip CMOS OLED/PLED driver with controller for organic/polymer light emitting diode dot-matrix graphic
display system. SH1106 consists of 132 segments, 64 commons that can support a maximum display resolution of 132 X 64. It
is designed for Common Cathode type OLED panel.
SH1106 embeds with contrast control, display RAM oscillator and efficient DC-DC converter, which reduces the number of
external components and power consumption. SH1106 is suitable for a wide range of compact portable applications, such as
sub-display of mobile phone, calculator and MP3 player, etc.
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SH1106 pdf, 数据表
SH1106
Functional Description
Microprocessor Interface Selection
The 8080-Parallel Interface, 6800-Parallel Interface, Serial Interface (SPI) or I2C Interface can be selected by different
selections of IM0~2 as shown in Table 1.
Table. 1
Config
Data signal
Control signal
Interface
IM0 IM1 IM2 D7 D6 D5 D4 D3 D2 D1 D0 E/ RD WR CS A0 RES
6800
0 0 1 D7 D6 D5 D4 D3 D2 D1 D0 E R / W CS A0 RES
8080
0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 RD WR CS A0 RES
4-Wire SPI 0 0 0
Pull Low
SI SCL
Pull Low
A0 RES
3-Wire SPI 1 0 0
Pull Low
SI SCL
Pull Low
RES
I2C 0 1 0
Pull Low
SDA SCL
Pull Low
SA0 RES
6800-series Parallel Interface
The parallel interface consists of 8 bi-directional data pads (D7-D0), WR ( R / W ), RD (E), A0 and CS . When WR ( R / W ) =
“H”, read operation from the display RAM or the status register occurs. When WR ( R / W ) = “L”, Write operation to display data
RAM or internal command registers occurs, depending on the status of A0 input. The RD (E) input serves as data latch signal
(clock) when it is “H”, provided that CS = “L” as shown in Table. 2.
Table. 2
IM0 IM1 IM2
Type
CS A0 RD WR
D0 to D7
0 0 1 6800 microprocessor bus CS
A0
E R/W
D0 to D7
In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processing are
internally performed, which require the insertion of a dummy read before the first actual display data read. This is shown in
Figure. 1 below.
A0
MPU
E
R/W
DATA
N N n n+1
Address preset
Internal
timing
Read signal
Column address
BUS holder
Preset
N
N
Incremented
N+1
n
N+2
n+1
n+2
Set address n
Dummy read
Figure. 1
Data Read
address n
Data Read
address n+1
8
V0.2







SH1106 equivalent, schematic
Page Address
D3 D2 D1 D0
0000
D3 D2 D1 D0
0001
D3 D2 D1 D0
0010
D3 D2 D1 D0
0011
D3 D2 D1 D0
0100
D3 D2 D1 D0
0101
D3 D2 D1 D0
0110
D3 D2 D1 D0
0111
Data
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
PAGE 0
PAGE1
PAGE2
PAGE3
PAGE4
PAGE5
PAGE6
PAGE7
Line Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
SH1106
OUTPUT
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
Figure. 8
16
V0.2










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