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PDF ( 数据手册 , 数据表 ) ATmega1284RFR2

零件编号 ATmega1284RFR2
描述 8-bit Microcontroller
制造商 ATMEL Corporation
LOGO ATMEL Corporation LOGO 


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ATmega1284RFR2 数据手册, 描述, 功能
ATmega2564/1284/644RFR2
Features
Network support by hardware assisted Multiple PAN Address Filtering
Advanced Hardware assisted Reduced Power Consumption
High Performance, Low Power AVR® 8-Bit Microcontroller
Advanced RISC Architecture
- 135 Powerful Instructions – Most Single Clock Cycle Execution
- 32x8 General Purpose Working Registers / On-Chip 2-cycle Multiplier
- Up to 16 MIPS Throughput at 16 MHz and 1.8V – Fully Static Operation
Non-volatile Program and Data Memories
- 256K/128K/64K Bytes of In-System Self-Programmable Flash
Endurance: 10’000 Write/Erase Cycles @ 125°C (25’000 Cycles @ 85°C)
- 8K/4K/2K Bytes EEPROM
Endurance: 20’000 Write/Erase Cycles @ 125°C (100’000 Cycles @ 25°C)
- 32K/16K/8K Bytes Internal SRAM
JTAG (IEEE std. 1149.1 compliant) Interface
- Boundary-scan Capabilities According to the JTAG Standard
- Extensive On-chip Debug Support
- Programming of Flash EEPROM, Fuses and Lock Bits through the JTAG interface
Peripheral Features
- Multiple Timer/Counter & PWM channels
- Real Time Counter with Separate Oscillator
- 10-bit, 330 ks/s A/D Converter; Analog Comparator; On-chip Temperature Sensor
- Master/Slave SPI Serial Interface
- Two Programmable Serial USART
- Byte Oriented 2-wire Serial Interface
Advanced Interrupt Handler and Power Save Modes
Watchdog Timer with Separate On-Chip Oscillator
Power-on Reset and Low Current Brown-Out Detector
Fully integrated Low Power Transceiver for 2.4 GHz ISM Band
- High Power Amplifier support by TX spectrum side lobe suppression
- Supported Data Rates: 250 kb/s and 500 kb/s, 1 Mb/s, 2 Mb/s
- -100 dBm RX Sensitivity; TX Output Power up to 3.5 dBm
- Hardware Assisted MAC (Auto-Acknowledge, Auto-Retry)
- 32 Bit IEEE 802.15.4 Symbol Counter
- SFD-Detection, Spreading; De-Spreading; Framing ; CRC-16 Computation
- Antenna Diversity and TX/RX control / TX/RX 128 Byte Frame Buffer
PLL synthesizer with 5 MHz and 500 kHz channel spacing for 2.4 GHz ISM Band
Hardware Security (AES, True Random Generator)
Integrated Crystal Oscillators (32.768 kHz & 16 MHz, external crystal needed)
I/O and Package
- 33 Programmable I/O Lines
- 48-pad QFN (RoHS/Fully Green)
Temperature Range: -40°C to 125°C Industrial
Ultra Low Power consumption (1.8 to 3.6V) for AVR & Rx/Tx: 10.1mA/18.6 mA
- CPU Active Mode (16MHz): 4.1 mA
- 2.4GHz Transceiver: RX_ON 6.0 mA / TX 14.5 mA (maximum TX output power)
- Deep Sleep Mode: <700nA @ 25°C
Speed Grade: 0 – 16 MHz @ 1.8 – 3.6V range with integrated voltage regulators
8-bit
Microcontroller
with Low Power
2.4GHz
Transceiver for
ZigBee and
IEEE 802.15.4
ATmega2564RFR2
ATmega1284RFR2
ATmega644RFR2
Applications
ZigBee® / IEEE 802.15.4-2011/2006/2003– Full and Reduced Function Device
General Purpose 2.4GHz ISM Band Transceiver with Microcontroller
RF4CE, SP100, WirelessHART, ISM Applications and IPv6 / 6LoWPAN
42073B-MCU Wireless-09/14
42073B-MCU Wireless-09/14
1







ATmega1284RFR2 pdf, 数据表
3.4.5 Port G2
The port G2 is not connected to a pin in the ATmega2564/1284/644RFR2. The
alternate pin function AMR (asynchronous automated meter reading input to timer 2) is
not available.
3.4.6 Port G5
The port G5 is not connected to a pin in the ATmega2564/1284/644RFR2. The
alternate pin function OC0B (output compare channel of 8-Bit timer 0) is not available.
3.4.7 RSTON
The RSTON reset output signaling the internal reset state is not connected to a pin in
the ATmega2564/1284/644RFR2.
4 Resources
A comprehensive set of development tools and application notes, and datasheets are
available for download on http://www.atmel.com.
5 About Code Examples
This documentation contains simple code examples that briefly show how to use
various parts of the device. Be aware that not all C compiler vendors include bit
definitions in the header files and interrupt handling in C is compiler dependent. Please
confirm with the C compiler documentation for more details.
These code examples assume that the part specific header file is included before
compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC",
"CBI", and "SBI" instructions must be replaced with instructions that allow access to
extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and
"CBR".
6 Data Retention and Endurance
6.1 Data Retention
The data retention of the non-volatile memories is
over 10 years at 125°C
over 100 years at 25°C
6.2 Endurance of the Code Memory (FLASH)
The endurance of the code memory (FLASH) is
125°C – 10,000 Write/Erase cycles
85°C – 25,000 Write/Erase cycles
6.3 Endurance of the Data Memory (EEPROM)
The endurance of the entire data memory (EEPROM) is
125°C – 20,000 Write/Erase cycles
85°C – 50,000 Write/Erase cycles
25°C – 100,000 Write/Erase cycles
8 ATmega2564/1284/644RFR2
42073B-MCU Wireless-09/14







ATmega1284RFR2 equivalent, schematic
interrupts are assigned individual enable bits which must be written logic one together
with the Global Interrupt Enable bit in the Status Register in order to enable the
interrupt. Depending on the Program Counter value, interrupts may be automatically
disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves
software security. See the section "Memory Programming" on page 502 for details.
The lowest addresses in the program memory space are by default defined as the
Reset and Interrupt Vectors. The complete list of vectors is shown in "Interrupts" on
page 241. The list also determines the priority levels of the different interrupts. The
lower the address the higher is the priority level. RESET has the highest priority, and
next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to
the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register
(MCUCR). Refer to "Interrupts" on page 241 for more information. The Reset Vector
can also be moved to the start of the Boot Flash section by programming the
BOOTRST Fuse, see "Memory Programming" on page 502.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts
are disabled. The user software can write logic one to the I-bit to enable nested
interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit
is automatically set when a Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that
sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the
actual Interrupt Vector in order to execute the interrupt handling routine, and hardware
clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a
logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while
the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and
remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if
one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared,
the corresponding Interrupt Flag(s) will be set and remembered until the Global
Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present.
These interrupts do not necessarily have Interrupt Flags. If the interrupt condition
disappears before the interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and
execute one more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt
routine, nor restored when returning from an interrupt routine. This must be handled by
software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately
disabled. No interrupt will be executed after the CLI instruction, even if it occurs
simultaneously with the CLI instruction. The following example shows how this can be
used to avoid interrupts during the timed EEPROM write sequence.
Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMPE ; start EEPROM write
sbi EECR, EEPE
out SREG, r16 ; restore SREG value (I-bit)
16 ATmega2564/1284/644RFR2
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