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PDF ( 数据手册 , 数据表 ) RTL8180L

零件编号 RTL8180L
描述 WIRELESS LAN NETWORK INTERFACE CONTROLLER
制造商 Realtek
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RTL8180L 数据手册, 描述, 功能
RTL8180L
REALTEK WIRELESS LAN
NETWORK INTERFACE CONTROLLER
RTL8180
1. Features............................................................................ 2
2. General Description ........................................................ 3
3. Block Diagram................................................................. 4
4. Pin Assignments............................................................... 5
5. Pin Descriptions............................................................... 6
5.1 Power Management/Isolation Interface ...................... 6
5.2 PCI Interface .............................................................. 7
5.3 EEPROM Interface..................................................... 8
5.4 Power Pins.................................................................. 9
5.5 LED Interface ............................................................. 9
5.6 Attachment Unit Interface ........................................ 10
5.6.1 Intersil RF Chipset ............................................ 10
5.6.2 RFMD RF Chipset ........................................... 12
5.6.3 Philips RF Chipset ............................................ 13
5.7 Test, Clock and Other Pins....................................... 14
6. Register Descriptions .................................................... 15
6.1 TSFTR:TimingSynchronizationFunctionTimerRegister....... 17
6.2 BRSR: Basic Rate Set Register ................................ 17
6.3 BSSID: Basic Service Set ID ................................... 17
6.4 CR: Command Register............................................ 18
6.5 IMR: Interrupt Mask Register .................................. 19
6.6 ISR: Interrupt Status Register................................... 20
6.7 TCR: Transmit Configuration Register .................... 21
6.8 RCR: Receive Configuration Register...................... 22
6.9 9346CR: 93C46 (93C56) Command Register .......... 24
6.10 CONFIG 0: Configuration Register 0..................... 25
6.11 CONFIG 1: Configuration Register 1..................... 26
6.12 CONFIG 2: Configuration Register 2..................... 27
6.13 MSR: Media Status Register .................................. 27
6.14 CONFIG 3: Configuration Register 3..................... 28
6.15 CONFIG 4: Configuration Register 4..................... 29
6.16 PSR: Page Select Register ...................................... 30
6.17 SCR: Security Configuration Register.................... 30
6.18 BcnItv: Beacon Interval Register ........................... 31
6.19 AtimWnd: Atim Window Register ......................... 31
6.20 BintrItv: Beacon Interrupt Interval Register........... 31
6.21 AtimtrItv: Atim Interrupt Interval Register ............ 31
6.22 PhyDelay: Phy Delay Register ............................... 32
6.23 DK0: Default Key 0 Register ................................. 32
6.24 DK1: Default Key 1 Register ................................. 32
6.25 DK2: Default Key 2 Register ................................. 32
6.26 DK3: Default Key 3 Register ................................. 33
6.27 CONFIG 5: Configuration Register 5..................... 33
6.28 TPPoll: Transmit Priority Polling Register............. 34
6.29 CWR: Contention Window Register ...................... 35
6.30 RetryCTR: Retry Count Register............................ 35
6.31 RDSAR: Receive Descriptor Start Address Register .... 35
6.32 FER: Function Event Register ................................ 35
6.33 FEMR: Function Event Mask Register................... 36
6.34 FPSR: Function Present State Register................... 36
6.35 FFER: Function Force Event Register.................... 37
7. EEPROM (93C46 or 93C56) Contents........................ 38
7.1 Summary of RTL8180 EEPROM Registers ............. 40
7.2 Summary of EEPROM Power Management Registers ... 40
8. PCI Configuration Space Registers ............................. 41
8.1 PCI Bus Interface ..................................................... 41
8.1.1 Interrupt Control ............................................... 41
8.1.2 Latency Timer ................................................... 41
8.2 Bus Operation........................................................... 42
8.2.1 Target Read....................................................... 42
8.2.2 Target Write...................................................... 43
8.2.3 Master Read ...................................................... 44
8.2.4 Master Write ..................................................... 45
8.2.5 Configuration Access ........................................ 45
8.3 Packet Buffering ....................................................... 46
8.3.1 Transmit Buffer Manager.................................. 46
8.3.2 Receive Buffer Manager ................................... 46
8.3.3 Packet Recognition ........................................... 46
8.4 PCI Configuration Space Table ................................ 47
8.5 PCI Configuration Space Functions.......................... 49
8.6 Default Value After Power-on (RSTB Asserted)............ 53
8.7 PCI Power Management Functions........................... 54
8.8 VPD (Vital Product Data) ........................................ 55
9. Functional Description.................................................. 56
9.1 Transmit & Receive Operations ............................... 56
9.1.1 Transmit ............................................................ 56
9.1.2 Receive.............................................................. 61
9.2 Loopback Operation ................................................. 64
9.3 Tx Encapsulation ...................................................... 64
9.4 Rx Decapsulation...................................................... 64
9.5 Memory Functions.................................................... 65
9.5.1 Memory Read Line (MRL) ............................... 65
9.5.2 Memory Read Multiple (MRM)........................ 65
9.5.3 Memory Write and Invalidate (MWI) ............... 66
9.6 LED Functions.......................................................... 67
9.6.1 Link Monitor ..................................................... 67
9.6.2 Infrastructure Monitor....................................... 67
9.6.3 Rx LED ............................................................. 67
9.6.4 Tx LED ............................................................. 68
9.6.5 Tx/Rx LED........................................................ 68
9.6.6 LINK/ACT LED ............................................... 69
10. Application Diagram................................................... 70
11. Electrical Characteristics............................................ 71
11.1 Temperature Limit Ratings ..................................... 71
11.2 DC Characteristics.................................................. 71
11.3 AC Characteristics.................................................. 72
11.3.1 Serial EEPROM Interface Timing .................. 72
11.3.2 PCI Bus Operation Timing.............................. 73
11.3.3 Serial Interface Timing ................................... 81
11.3.4 RF Control Timing.......................................... 82
12. Mechanical Dimensions............................................... 84
2003/3/31
1
Rev1.2







RTL8180L pdf, 数据表
IRDYB
S/T/S
17
TRDYB
S/T/S
20
PAR T/S 25
PERRB
S/T/S
23
SERRB
O/D
24
STOPB
RSTB
S/T/S
I
22
112
5.3 EEPROM Interface
Symbol
EESK
EEDI
EEDO
EECS
Type
O
O
O/I
O
Pin No
103
102
101
104
RTL8180L
Initiator Ready: This indicates the initiating agents ability to complete
the current data phase of the transaction.
As a bus master, this signal will be asserted low when the RTL8180 is
ready to complete the current data phase transaction. This signal is used in
conjunction with the TRDYB signal. Data transaction takes place at the
rising edge of CLK when both IRDYB and TRDYB are asserted low. As a
target, this signal indicates that the master has put data on the bus.
Target Ready: This indicates the target agents ability to complete the
current phase of the transaction.
As a bus master, this signal indicates that the target is ready for the data
during write operations and with the data during read operations. As a
target, this signal will be asserted low when the (slave) device is ready to
complete the current data phase transaction. This signal is used in
conjunction with the IRDYB signal. Data transaction takes place at the
rising edge of CLK when both IRDYB and TRDYB are asserted low.
Parity: This signal indicates even parity across AD31-0 and C/BE3-0,
including the PAR pin. PAR is stable and valid one clock after each
address phase. For data phases, PAR is stable and valid one clock after
either IRDYB is asserted on a write transaction or TRDYB is asserted on
a read transaction. Once PAR is valid, it remains valid until one clock
after the completion of the current data phase. As a bus master, PAR is
asserted during address and write data phases. As a target, PAR is
asserted during read data phases.
Parity Error: This pin is used to report data parity errors during all PCI
transactions except a Special Cycle. PERRB Is driven active (low) two
clocks after a data parity error is detected by the device receiving data,
and the minimum duration of PERRB is one clock for each data phase
with parity error detected.
System Error: If an address parity error is detected and Configuration
Space Status register bit 15 (detected parity error) is enabled, the
RTL8180 asserts the SERRB pin low and bit 14 of Status register in
Configuration Space.
Stop: Indicates that the current target is requesting the master to stop the
current transaction.
Reset: When RSTB is asserted low, the RTL8180 performs an internal
system hardware reset. RSTB must be held for a minimum of 120 ns.
Description
EESK in 93C46 (93C56) programming or auto-load mode.
EEDI in 93C46 (93C56) programming or auto-load mode.
EEDO in 93C46 (93C56) programming or auto-load mode.
EEPROM Chip Select: 93C46 (93C56) chip select
2003/3/31
8
Rev1.2







RTL8180L equivalent, schematic
005Bh
005Ch-005Dh
005Eh
005Fh
0060h-006Fh
0070h-0071h
0072h-0073h
0074h-0075h
0076h-0077h
0078h
0079h
007Ah-007Bh
007Ch
007Dh
007Eh
0080h-0083h
0084h008Bh
008Ch0093h
0094h009Bh
009Ch00A3h
00A4h00ABh
00ACh00B3h
00B4h00BBh
00BCh00C3h
00C4h-00C5h
00C6h-00C7h
00C8h-00C9h
00CAh-00CBh
00CCh-00CDh
00CEh-00D3h
0084h-008Fh
0090h-009Fh
00A0h-00AFh
00B0h-00Bfh
00C0h-00CFh
00D0h-00D3h
00D4h-00D7h
00D8h
00D9h
00DAh-00DBh
00DCh-00DDh
00DEh
00DFh-00E3h
00E4h-00E7h
00E8h-00EFh
00F0h-00F3h
00F4h-00F7h
00F8h-00FBh
00FCh-00FFh
RTL8180L
R/W
TESTR
TEST mode Register
- - Reserved
R/W PSR Page Select Register
R/W SCR Security Configuration Register
- - Reserved
R/W
BcnItv
Beacon Interval Register
R/W
AtimWnd
Atim Window Register
R/W
BintrItv
Beacon interrupt Interval Register
R/W
AtimtrItv
Atim interrupt Interval Register
R/W
PhyDelay
Phy Delay Register
R/W
CRCount
Carrier Sense Counter
- - Reserved
R/W
PhyAddr
Address register for Phy interface
W
PhyDataW
Write Data to Phy
R
PhyDataR
Read Data from Phy
R/W
PhyCFG
Phy Configuration Register
0084h-00D3h is slected to page 1 when PSEn bit (bit 0, PSR) is set to 1
R/W
Wakeup0
Power Management wakeup frame0 (64-bit)
R/W
Wakeup1
Power Management wakeup frame1 (64-bit)
R/W
Wakeup2LD
Power Management wakeup frame2 (128-bit), low D-Word
R/W
Wakeup2HD
Power Management wakeup frame2, high D-Word
R/W
Wakeup3LD
Power Management wakeup frame3 (128-bit), low D-Word
R/W
Wakeup3HD
Power Management wakeup frame3, high D-Word
R/W
Wakeup4LD
Power Management wakeup frame4 (128-bit), low D-Word
R/W
Wakeup4HD
Power Management wakeup frame4, high D-Word
R/W
CRC0
16-bit CRC of wakeup frame 0
R/W
CRC1
16-bit CRC of wakeup frame 1
R/W
CRC2
16-bit CRC of wakeup frame 2
R/W
CRC3
16-bit CRC of wakeup frame 3
R/W
CRC4
16-bit CRC of wakeup frame 4
- - Reserved
0084h-00D3h is slected to page 0 when PSEn bit (bit 0, PSR) is set to 0
R/W - Reserved
R/W DK0 Default Key 0 Register
R/W DK1 Default Key 1 Register
R/W DK2 Default Key 2 Register
R/W DK3 Default Key 3 Register
- - Reserved
- - Reserved
R/W
CONFIG5
Configuration Register 5
W
TPPoll
Transmit Priority Polling Register
- - Reserved
R
CWR
Contention Window Register
R
RetryCTR
Retry Count Register
- - Reserved
R/W
RDSAR
Receive Descriptor Start Address Register (32-bit) (256-byte alignment)
- - Reserved
R/W FER Function Event Register (CardBus only)
R/W
FEMR
Function Event Mask Register (CardBus only)
R
FPSR
Function Present State Register (CardBus only)
W
FFER
Function Force Event Register (CardBus only)
2003/3/31
16
Rev1.2










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