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PDF ( 数据手册 , 数据表 ) 83C152JC

零件编号 83C152JC
描述 Universal Communication Controller 8-Bit Microcontroller
制造商 Intel
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83C152JC 数据手册, 描述, 功能
8XC152JA JB JC JD
UNIVERSAL COMMUNICATION CONTROLLER
8-BIT MICROCONTROLLER
X 8K Factory Mask Programmable ROM Available
Y Superset of 80C51 Architecture
Y Multi-Protocol Serial Communication
I O Port (2 048 Mbps 2 4 Mbps Max)
SDLC HDLC Only
CSMA CD and SDLC HDLC
User Definable Protocols
Y Full Duplex Half Duplex
Y MCS -51 Compatible UART
Y 16 5 MHz Maximum Clock Frequency
Y Multiple Power Conservation Modes
Y 64KB Program Memory Addressing
Y 64KB Data Memory Addressing
Y 256 Bytes On-Chip RAM
Y Dual On-Chip DMA Channels
Y Hold Hold Acknowledge
Y Two General Purpose Timer Counters
Y 5 or 7 I O Ports
Y 56 Special Function Registers
Y 11 Interrupt Sources
Y Available in 48 Pin Dual-in-Line Package
and 68 Pin Surface Mount PLCC
Package
(See Packaging Spec Order 231369)
The 80C152 which is based on the MCS -51 CPU is a highly integrated single-chip 8-bit microcontroller
designed for cost-sensitive high-speed serial communications It is well suited for implementing Integrated
Services Digital Networks (ISDN) emerging Local Area Networks and user defined serial backplane applica-
tions In addition to the multi-protocol communication capability the 80C152 offers traditional microcontroller
features for peripheral I O interface and control
Silicon implementations are much more cost effective than multi-wire cables found in board level parallel-to-
serial and serial-to-parallel converters The 83C152 contains in silicon all the features needed for the serial-
to-parallel conversion Other 83C152 benefits include 1) better noise immunity through differential signaling or
fiber optic connections 2) data integrity utilizing the standard designed in CRC checks and 3) better modulari-
ty of hardware and software designs All of these cost network parameter and real estate improvements
apply to 83C152 serial links between boards or systems and 83C152 serial links on a single board
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
October 1989
Order Number 270431-003







83C152JC pdf, 数据表
8XC152JA JB JC JD
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature Under Bias 0 C to a70 C
Storage Temperature
b65 C to a150 C
Voltage on Any pin to VSS
Voltage on VCC to VSS
Power Dissipation
b0 5V to (VCC a 0 5V)
b0 5V to a6 5V
1 0W(9)
NOTICE This data sheet contains preliminary infor-
mation on new products in production The specifica-
tions are subject to change without notice Verify with
your local Intel Sales office that you have the latest
data sheet before finalizing a design
WARNING Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage
These are stress ratings only Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability
D C CHARACTERISTICS (TA e 0 C to a70 C VCC e 5V g10% VSS e 0V)
Symbol
Parameter
Min
Typ
(Note 3)
Max
Unit Test Conditions
VIL Input Low Voltage
(All Except EA EBEN)
b0 5
0 2VCCb0 1 V
VIL1 Input Low Voltage
(EA EBEN)
VIH Input High Voltage
(Except XTAL1 RST)
b0 5
0 2VCCa0 9
0 2VCCb0 3 V
VCCa0 5 V
VIH1
Input High Voltage
(XTAL1 RST)
0 7VCC
VCCa0 5 V
VOL Output Low Voltage
(Ports 1 2 3 4 5 6)
0 45
V
IOL e 1 6 mA
(Note 4)
VOL1 Output Low Voltage
(Port 0 ALE PSEN EPSEN)
0 45
V
IOL e 3 2 mA
(Note 4)
VOH
VOH1
IIL
Output High Voltage
(Ports 1 2 3 4 5 6 COMM9
ALE PSEN EPSEN)
Output High Voltage
(Port 0 in External
Bus Mode)
Logical 0 Input
Current (Ports 1 2 3 4 5 6)
24
0 9VCC
24
0 9VCC
b50
V IOH e b60 mA
VCC e 5V g10%
V IOH e b10 mA
V IOH e b400 mA
VCC e 5V g10%
V IOH e b40 mA (Note 5)
mA VIN e 0 45V
ITL Logical 1 to 0
Transition Current
(Ports 1 2 3 4 5 6)
b650 mA
VIN e 2V
ILI
RRST
Input Leakage
(Port 0 EA)
Reset Pullup Resistor
40
g10 mA 0 45kVINkVCC
kX
IIH Logical 1 Input Current (EBEN)
ICC Power Supply Current
Active (16 5 MHz)
Idle (16 5 MHz)
Power Down Mode
a60
mA
31
41 1
mA (Note 6)
8
15 4
mA (Note 6)
10 mA VCC e 2 0V to 5 5V
8







83C152JC equivalent, schematic
8XC152JA JB JC JD
GSC TIMINGS (EXTERNAL CLOCK)
270431 – 17
NOTES
1 N C pins on PLCC package may be connected to internal die and should not be used in customer applications
2 It is recommended that both Pin 3 and Pin 33 be grounded for PLCC devices
3 ‘‘Typicals’’ are based on samples taken from early manufacturing lots and are not guaranteed The measurements were
made with VCC e 5V at room temperature
4 Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports
1 and 3 The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-
to-0 transitions during bus operations In the worst cases (capacitive loading l 100 pF) the noise pulse on the ALE pin may
exceed 0 8V In such cases it may be desirable to qualify ALE with a Schmitt Trigger or use an address latch with a Schmitt
Trigger STROBE input
5 Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0 9VCC specifi-
cation when the address bits are stabilizing
6 ICC is measured with all output pins disconnected XTAL1 driven with TCLCH TCHCL e 5 ns VIL e VSS a 0 5V VIH e
VCC b 0 5V XTAL2 N C Port 0 pins connected to VCC ‘‘Operating’’ current is measured with EA connected to VCC and
RST connected to VSS ‘‘Idle’’ current is measured with EA connected to VSS RST connected to VCC and GSC inactive
7 The specifications relating to external data memory characteristics are also applicable to DMA operations
8 TQVWX should not be confused with TQVWX as specified for 80C51BH On 80C152 TQVWX is measured from data
valid to rising edge of WR On 80C51BH TQVWX is measured from data valid to falling edge of WR See timing diagrams
9 This value is based on the maximum allowable die temperature and the thermal resistance of the package
10 All specifications relating to external program memory characteristics are applicable to
EPSEN for PSEN
Port 5 for Port 0
Port 6 for Port 2
when EBEN is at a Logical 1 on the 80C152JB JD
11 Same as TCLCH use External Clock Drive Waveform
12 Same as TCHCL use External Clock Drive Waveform
13 When using the same external clock to drive both the receiver and transmitter the minimum ECL spec effectively
becomes 195 ns at all frequencies (assuming 0 ns propagation delay) because ECDVT (150 ns) plus ECDSR (45 ns) re-
quirements must also be met (150 a 45 e 195 ns) The 195 ns requirement would also increase to include the maximum
propagation delay between receivers and transmitters
16










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