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PDF ( 数据手册 , 数据表 ) 74HCT165

零件编号 74HCT165
描述 8-bit parallel-in/serial out shift register
制造商 NXP Semiconductors
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74HCT165 数据手册, 描述, 功能
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
Rev. 03 — 14 March 2008
Product data sheet
1. General description
The 74HC165; 74HCT165 are high-speed Si-gate CMOS devices that comply with
JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL).
The 74HC165; 74HCT165 are 8-bit parallel-load or serial-in shift registers with
complementary serial outputs (Q7 and Q7) available from the last stage. When the
parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the
register asynchronously.
When PL is HIGH, data enters the register serially at the DS input and shifts one place to
the right (Q0 Q1 Q2, etc.) with each positive-going clock transition. This feature
allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the
succeeding stage.
The clock input is a gated-OR structure which allows one input to be used as an active
LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE
should only take place while CP HIGH for predictable operation. Either the CP or the CE
should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data
when PL is activated.
2. Features
I Asynchronous 8-bit parallel load
I Synchronous serial input
I Complies with JEDEC standard no. 7A
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C
3. Applications
I Parallel-to-serial data conversion







74HCT165 pdf, 数据表
NXP Semiconductors
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
11. Dynamic characteristics
Table 7. Dynamic characteristics
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12
Symbol Parameter Conditions
25 °C
40 °C to +85 °C 40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
74HC165
tpd propagation CP or CE to Q7, Q7;
delay
see Figure 7
[1]
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 5.0 V; CL = 15 pF
PL to Q7, Q7; see Figure 8
- 52 165 - 205 -
- 19 33
-
41
-
- 15 28
-
35
-
- 16 -
-
-
-
250 ns
50 ns
43 ns
- ns
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 5.0 V; CL = 15 pF
D7 to Q7, Q7; see Figure 9
- 50 165 - 205 -
- 18 33
-
41
-
- 14 28
-
35
-
- 15 -
-
-
-
250 ns
50 ns
43 ns
- ns
VCC = 2.0 V
- 36 120 - 150 -
180 ns
VCC = 4.5 V
- 13 24
-
30
-
36 ns
VCC = 6.0 V
- 10 20
-
26
-
31 ns
VCC = 5.0 V; CL = 15 pF
- 11 -
-
-
-
- ns
tt
transition
Q7, Q7 output; see Figure 7 [2]
time VCC = 2.0 V
- 19 75
-
95
-
110 ns
VCC = 4.5 V
- 7 15
-
19
-
22 ns
VCC = 6.0 V
- 6 13
-
16
-
19 ns
tW pulse width CP input HIGH or LOW;
see Figure 7
VCC = 2.0 V
80 17 - 100
-
120
- ns
VCC = 4.5 V
16 6 -
20
-
24
- ns
VCC = 6.0 V
14 5 -
17
-
20
- ns
PL input LOW; see Figure 8
VCC = 2.0 V
80 14 - 100
-
120
- ns
VCC = 4.5 V
16 5 -
20
-
24
- ns
VCC = 6.0 V
14 4 -
17
-
20
- ns
trec recovery time PL to CP, CE; see Figure 8
VCC = 2.0 V
100 22 - 125
-
150
- ns
VCC = 4.5 V
20 8 -
25
-
30
- ns
VCC = 6.0 V
17 6 -
21
-
26
- ns
74HC_HCT165_3
Product data sheet
Rev. 03 — 14 March 2008
© NXP B.V. 2008. All rights reserved.
8 of 22







74HCT165 equivalent, schematic
NXP Semiconductors
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
y
Z
16
D
pin 1 index
1
e
EA
X
c
HE
vM A
9
A2
A1
8
bp
wM
Q
(A3)
A
Lp
L
detail X
θ
0 2.5 5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
UNIT max. A1 A2 A3 bp
c
D (1) E (1)
e
HE
L
Lp
Q
v
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
inches
0.069
0.010
0.004
0.057
0.049
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.05
0.244
0.228
0.041
0.039
0.016
0.028
0.020
0.01
w y Z (1)
0.25 0.1
0.7
0.3
0.01
0.004
0.028
0.012
θ
8o
0o
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
OUTLINE
VERSION
SOT109-1
IEC
076E07
REFERENCES
JEDEC
JEITA
MS-012
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 14. Package outline SOT109-1 (SO16)
74HC_HCT165_3
Product data sheet
Rev. 03 — 14 March 2008
© NXP B.V. 2008. All rights reserved.
16 of 22










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