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PDF ( 数据手册 , 数据表 ) 71M6513H

零件编号 71M6513H
描述 Power Meter IC
制造商 TDK
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71M6513H 数据手册, 描述, 功能
GENERAL DESCRIPTION
71M6513/71M6513H
Power Meter IC
PRELIMINARY DATASHEET
SEPTEMBER 2004
FEATURES
The TDK 71M6513 is a highly integrated SOC with an MPU core,
RTC, FLASH and LCD driver. TDK’s patent pending Single Con-
verter Technology with a 21-bit delta-sigma ADC, 6 analog
inputs, digital temperature compensation, precision voltage
reference and 32-bit computation engine support a wide range of
polyphase metering applications with very few low cost external
components. A 32kHz crystal timebase for the entire system and
internal battery backup support for RAM and RTC further reduce
system cost.
Maximum design flexibility is supported with multiple UARTs, I2C,
power fail comparator, 5V LCD charge pump, up to 22 DIO pins and
in system programmable FLASH which can be updated with data or
application code in operation. Easy conversion to ROM offers un-
precedented cost structure for high volume applications. The device
is offered in high (0.1%) and low (0.5%) accuracy versions for multi-
function residential/commercial meter applications requiring multiple
voltage/current inputs, larger LCD or DIO features.
A complete array of ICE and development tools, programming
libraries and reference designs enable rapid development and
certification of meters that meet most demanding world wide
electricity metering standards.
LIVE
NEUT
LIVE
CT /COIL
LIVE
LOAD
POWER SUPPLY
AMR
IR
POWER
FAULT
etc.
CONVERTER
IA
VA
IB
VB
IC
VC
VOLTAGE REF
VREF
VBIAS
SERIAL PORTS
TX
RX
SENSE RX
DRIVE TX
COMPARATOR
V1
V2
V3
V3.3A V3.3D GNDA GNDD
5V BOOST
TDK
VDRV
71M6513 REGULATOR
VBAT
V2.5
TEMP
SENSOR
LCD DRIVER
DIO, PULSE
RAM
COMPUTE
ENGINE
VLCD
COM0..3
SEG0..23
SEG 24..27
DIO 4..11
FLASH/
ROM
SEG 32..41
DIO 12..21
MPU
RTC
TIMERS
ICE
DIO 0..3
OSC/PLL
XIN
XOUT
BATTERY
3/5V LCD
88.88.8888
MISC
EEPROM
32 kHz
< 0.1% Wh accuracy over 2000:1
range (71M6513H version)
< 0.5% Wh accuracy over 2000:1
range (71M6513 version)
Exceeds IEC62053 / ANSIC12.20.
Voltage reference < 10ppm/°C spec
(71M6513H version), <50ppm/°C
(71M6513 version)
Six sensor inputs - VDD referenced
Four quadrant metering
Voltage angles -- phase sequence
Digital temperature compensation
21-bit delta-sigma ADC
Independent 32bit compute engine
Low jitter Wh/ VARh pulse outputs
40-70Hz line frequency range
Phase compensation (±7°)
Battery Backup for RAM and RTC
29mW @3.3V, 7.2µW back up.
Flash memory option with security
8-bit microcontroller (80515) - 1 clock
cycle per instruction
Integrated ICE for MPU debug
LCD driver (168 pixels)
High speed SSI serial output
RTC for time of use functions
Two Event counter/timers
Watchdog timer
Power fail monitor
Up to 22 general purpose I/O pins
64kB Flash or ROM
7kB RAM
Two UARTs for IR and AMR
Third software UART via DIO pins
100-lead Exposed Pad LQFP
package (epLQFP)
Rev 2.9
PRELIMINARY DATA SHEET
Page: 1 of 56







71M6513H pdf, 数据表
71M6513/71M6513H
Power Meter IC
PRELIMINARY DATASHEET
SEPTEMBER 2004
Analog Front End (AFE)
The AFE of the TDK 71M6513 Power Meter IC is comprised of an input multiplexer, a delta-sigma A/D converter,
and a voltage reference.
Input multiplexer: The input multiplexer supports up to six input signals that are applied to pins IA, VA, IB, VB,
and IC, VC of the device. Alternatively, it has the ability to select temperature (TEMP) and an additional monitor
input, V3. The ALT multiplexer selection is intended to be commanded infrequently (every second or so) by the
MPU. In order to prevent disruption of the voltage tracking PLL and any voltage allpass networks, VA, VB, and
VC are not replaced in the ALT selections. In some equations, currents must be delayed in allpass networks and
therefore can’t be replaced in the ALT selection. Table 1 details the regular and alternative MUX sequences.
In a typical application, IA, IB, IC are connected to current transformers that sense the current on each phase of
the line voltage. VA, VB, and VC are typically connected to voltage sensors through resistor dividers.
MUX Control: MUX advance, FIR filter initiation, and VREF chopping (using the CROSS signal - described
below) are controlled by the MUX_CTRL circuit. Additionally, MUX_CTRL launches each pass through the CE
program. MUX_CTRL is clocked by CK32, the 32768Hz clock from the PLL block. The behavior of MUX_CTRL
is governed by MUX_ALT, EQU, and MUX_DIV.
The MUX_ALT bit requests an alternative multiplexer frame. The bit may be asserted on any MPU cycle and may
be subsequently deasserted on any cycle including the next one. A rising edge on MUX_ALT will cause
MUX_CTRL to wait until the next multiplexer frame and implement a single alternate frame.
Another control input to the multiplexer is MUX_DIV. This signal can request 2, 3, 4, or 6 multiplexer states per
frame.
Delta-sigma A/D Converter: A single delta-sigma A/D converter digitizes the power inputs to the device. The
resolution of the ADC is programmable using the FIR_LEN register as shown in the I/O RAM section. ADC
resolution can be selected to be 21 bits (FIR_LEN=0), or 22 bits (FIR_LEN=1). Conversion time is two cycles of
CK32 with FIR_LEN = 0 and three cycles with FIR_LEN = 1. Accuracy and timing specifications inthis data sheet
are based on FIR_LEN = 0.
Initiation of each ADC conversion is controlled by MUX_CTRL as described previously. At the end of each ADC
conversion the FIR filter output data is stored into the CE RAM location determined by the multiplexer selection.
Table 2 details the RAM locations.
Table 2: RAM Locations for ADC Results
ADDRESS (HEX)
00
01
02
NAME
IA
VA
IB
DESCRIPTION
Phase A current
Phase A voltage
Phase B current
Rev 2.9
PRELIMINARY DATA SHEET
Page: 8 of 56







71M6513H equivalent, schematic
71M6513/71M6513H
Power Meter IC
PRELIMINARY DATASHEET
SEPTEMBER 2004
Memory
Flash Memory: The 71M6513 includes 64KB of on-chip flash memory. The flash memory primarily contains
MPU program code. It also contains images of the CE program code, CE coefficients, MPU RAM, and CONFIG
RAM. On power-up, before enabling the CE, the MPU copies these images to their respective memory locations.
The bit FLASH66Z (see I/O RAM table) defines the speed for accessing flash. To minimize supply current draw,
this bit should be set to 1.
Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence.
These special pattern/sequence requirements prevent inadevertent erasure of the flash memory.
The mass erase sequence is:
1. Write 1 to the FLSH_MEEN bit (SFR address 0xB2[1].
2. Write pattern 0xAA to FLSH_ERASE (SFR address 0x94)
Note: The mass erase cycle can only be initiated when the ICE port is enabled.
The page erase sequence is:
1. Write the page address to FLSH_PGADR (SFR address 0xB7[7:1]
2. Write pattern 0x55 to FLSH_ERASE (SFR address 0x94)
The MPU may write to the flash memory. This is one of the non-volatile storage options available to the user.
The other option, battery backed-up RAM, is the lower supply current option for non-volatile storage.
FLSH_PWE (flash program write enable) differentiates 80515 data store instructions (MOVX@DPTR,A) between
Flash and XRAM writes.
MPU RAM: The 71M6513 includes 2k-bytes of static RAM memory on-chip plus 256-bytes of internal RAM in the
MPU core. The 2k-bytes of RAM are used for data storage during MPU normal operations.
CE RAM: The CE RAM is the working memory of the CE. The MPU can read and write the CE RAM as the
primary means of data communication between the two processors.
Rev 2.9
PRELIMINARY DATA SHEET
Page: 16 of 56










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