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PDF ( 数据手册 , 数据表 ) AP0100CS

零件编号 AP0100CS
描述 High-Dynamic Range (HDR) Image Signal Processor
制造商 Aptina
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AP0100CS 数据手册, 描述, 功能
Aptina Confidential and Proprietary
Preliminary
AP0100CS HDR: Image Signal Processor (ISP)
Features
AP0100CS High-Dynamic Range (HDR) Image Signal
Processor (ISP)
AP0100CS Data Sheet
For the latest product data sheet revision, refer to Aptina’s Web site:www.aptina.com
Features
• Up to 1.2Mp (1280x960) Aptina sensor support
• 45 fps at 1.2Mp, 60 fps at 720p
• Optimized for operation with HDR sensors.
• Color and gamma correction
• Auto exposure, auto white balance, 50/60 Hz auto
flicker detection and avoidance
• Adaptive Local Tone Mapping (ALTM)
• Programmable Spatial Transform Engine (STE).
• Pre-rendered Graphical Overlay
• Two-wire serial programming interface (CCIS)
• Interface to low-cost Flash or EEPROM through SPI
bus (to configure and load patches, etc.)
• High-level host command interface
• Standalone operation supported
• Up to 5 GPIO
• Fail-safe IO
• Multi-Camera synchronization support
• Integrated video encoder for NTSC/PAL with overlay
capability and 10-bit I-DAC
Applications
• IP cam and CCTV - HD
• Enables CCTV -HD w/ MP sensor
Ordering Information
Table 1:
Available Part Numbers
Part Number
AP0100CSSL00APGA0-E
AP0100CSSL00APGA0
AP0100CSSL00APGAD-E
AP0100CSSL00APGAH-E
Description
100-ball VFBGA Package Part Samples
100-ball VFBGA Package Part
AP0100CS demo kit
AP0100CS headboard
Table 2:
Key Performance Parameters
Parameter
Primary camera
interfaces
Primary camera input
Output interface
Output format
Maximum resolution
NTSC output
PAL output
Input clock range
Supply voltage
Operating temp.
Power consumption
Value
Parallel and HiSPi
RAW12 Linear/RAW12, RAW14 (HiSPi
format only) Companded
Analog composite, up to 16-bit parallel
digital output
YUV422 8-bit,10-bit, and 10-, 12-bit
tone-mapped Bayer
1280x960 (1.2Mp)
720H x 487V
720H x 576V
6-30 MHz
VDDIO_S
1.8 or 2.8V nominal
VDDIO_H
2.5 or 3.3V nominal
VDD_REG
1.8V nominal
VDD 1.2V nominal
VDD_PLL
1.2V nominal
VDD_DAC
1.2V nominal
VDDIO_OTPM 2.5 or 3.3V nominal
VDDA_DAC
3.3V nominal
VDD_PHY
2.8V nominal
–30°C to +70°C
170 mW
PDF: 5895261839 / Source: 7801027569
AP0100CS_DS - Rev. B Pub. 8/12 EN
1 Aptina reserves the right to change products or specifications without notice.
©2012 Aptina Imaging Corporation All rights reserved.
‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Aptina without
notice. Products are only warranted by Aptina to meet Aptina’s production data sheet specifications.







AP0100CS pdf, 数据表
Aptina Confidential and Proprietary
Preliminary
AP0100CS HDR: Image Signal Processor (ISP)
System Interfaces
Figure 3:
Typical HiSPi Configuration
Sensor IO
power
1.8V
( R egulator
IP)
1 . 2 V ( R egulator OP)
P ower up C ore, P LL.
and DAC digital
DAC HiSPi
analog voltage
power
OTPM
power
Host IO
power
Sensor IO
power
VDDIO _S
M_S CLK
M_S DATA
EXTCLK_OUT
RESET_BAR_OUT
FV _IN
LV_IN
PIXCLK _IN
DIN [11:0]
TRIGGER_OUT
CLK_N CLK_P
DATA0_N DATA0_P
DATA1_N DATA1_P
G ND_REG
GND
VDDIO _H
S CLK
S DATA
S ADDR
EXTCLK
XTAL
S P I_CS_BAR
SPI_CLK
SPI_SDO
SPI_SDI
FV_OUT
LV_OUT
PIXCLK_OUT
D OUT[15:0]
DAC_POS
DAC_NEG
DAC_REF
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
TRST_BAR5
VDDIO_S6 VDD_REG4 LDO_OP4
VDDIO_OTPM VDDIO_H
VDDIO_DAC
VDDIO_PHY
HiSPi and Parallel Connection
When using the HiSPi interface, the user should connect the parallel interface to
VDDIO_S.
When using the parallel interface, the HiSPi interface and power supply (VDD_PHY) can
be left floating.
PDF: 5895261839 / Source: 7801027569
AP0100CS_DS - Rev. B Pub. 8/12 EN
8 Aptina reserves the right to change products or specifications without notice.
©2012 Aptina Imaging Corporation All rights reserved.







AP0100CS equivalent, schematic
Table 7:
Output States
Name
CLK_N
CLK_P
DATA0_N
DATA0_P
DATA1_N
DATA1_P
FV_OUT,
LV_OUT,
PIXCLK_OUT,
DOUT[15:0]
DAC_POS
DAC_NEG
DAC_REF
GPIO[5:2]
GPIO1
TRIGGER_OUT
TRST_BAR
Hardware States
Reset State
Disabled
Default State
Disabled
Hard Standby
Dependent on
interface used
Firmware States
Soft Standby
Dependent on
interface used
Streaming
Dependent on
interface used
Idle
Dependent on
interface used
Notes
Input. Will be disabled and can be left
floating
High-impedance Varied
Driven if used
Driven if used
Driven if used
Driven if used
Output. Default state dependent on
configuration
Varied
Varied
Driven if used
Driven if used
Driven if used
Driven if used
Output. Default state dependent on
configuration. Tie to ground if VDAC
not used
n/a n/a n/a n/a n/a n/a Input. Requires reference resistor. Tie
to ground if VDAC not used
High-impedance Input, then high- Driven if used
impedance
Driven if used
Driven if used
Driven if used
Input/Output. After reset these pins
are sampled as inputs as part of auto-
configuration.
High-impedance High-impedance High-impedance High-impedance High-impedance High-impedance
High-impedance High-impedance Driven if used Driven if used Driven if used Driven if used
n/a
n/a
(negated)
(negated)
(negated)
(negated)
Input. Must always be driven to a valid
logic level.










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