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PDF ( 数据手册 , 数据表 ) 74VHC126

零件编号 74VHC126
描述 Quad buffer/line driver
制造商 NXP Semiconductors
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74VHC126 数据手册, 描述, 功能
74VHC126; 74VHCT126
Quad buffer/line driver; 3-state
Rev. 01 — 13 August 2009
Product data sheet
1. General description
The 74VHC126; 74VHCT126 are high-speed Si-gate CMOS devices and are pin
compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7-A.
The 74VHC126; 74VHCT126 provide four non-inverting buffer/line drivers with 3-state
outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE).
A LOW-level at pin nOE causes the outputs to assume a high-impedance OFF-state.
The 74VHC126; 74VHCT126 are identical to the 74VHC125; 74VHCT125 but have active
HIGH output enable inputs.
2. Features
I Balanced propagation delays
I All inputs have Schmitt-trigger action
I Inputs accept voltages higher than VCC
I Input levels:
N The 74VHC126 operates with CMOS input level
N The 74VHCT126 operates with TTL input level
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Multiple package options
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C







74VHC126 pdf, 数据表
NXP Semiconductors
74VHC126; 74VHCT126
Quad buffer/line driver; 3-state
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2] tpd is the same as tPLH and tPHL.
[3] ten is the same as tPZL and tPZH.
[4] tdis is the same as tPLZ and tPHZ.
[5] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
11. Waveforms
nA input
VI
GND
VOH
nY output
VOL
VM
tPHL
VM
tPLH
mna237
Fig 6.
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Input to output propagation delays
nOE input
VI
GND
VCC
output
LOW- to - OFF
OFF- to - LOW
VOL
output
VOH
HIGH - to - OFF
OFF- to - HIGH
GND
VM
t PLZ
t PZL
t PHZ
VX
VY
outputs
enabled
VM
t PZH
outputs
disabled
VM
outputs
enabled
mna949
Fig 7.
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Enable and disable times
74VHC_VHCT126_1
Product data sheet
Rev. 01 — 13 August 2009
© NXP B.V. 2009. All rights reserved.
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