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PDF ( 数据手册 , 数据表 ) D70F3123

零件编号 D70F3123
描述 UPD70F3123
制造商 NEC
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D70F3123 数据手册, 描述, 功能
Preliminary User’s Manual
V850E/CA1TM ATOMIC
32-/16-bit Single-Chip Microcontroller
Hardware
µPD703123,
µPD70F3123
Document No. U14913EE1V0UM00
Date Published October 2001
NEC Corporation 2001
Printed in Germany







D70F3123 pdf, 数据表
4.7 Idle State Insertion Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
4.8 Bus Priority Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
4.9 Boundary Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
4.9.1 Program space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
4.9.2 Data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Chapter 5 Memory Access Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.1 SRAM, External ROM, External I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.1.2 SRAM connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
5.1.3 SRAM, external ROM, external I/O access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
5.2 Page ROM Controller (ROMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
5.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
5.2.2 Page ROM connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
5.2.3 On-page/off-page judgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
5.2.4 Page ROM configuration register (PRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
5.2.5 Page ROM access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Chapter 6 DMA Functions (DMA Controller) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
6.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
6.3 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
6.3.1 DMA source address registers 0 to 3 (DSA0 to DSA3) . . . . . . . . . . . . . . . . . . . . 165
6.3.2 DMA destination address registers 0 to 3 (DDA0 to DDA3) . . . . . . . . . . . . . . . . 167
6.3.3 DMA transfer count registers 0 to 3 (DBC0 to DBC3) . . . . . . . . . . . . . . . . . . . . . 169
6.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3) . . . . . . . . . . . . . . . 170
6.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3) . . . . . . . . . . . . . . . . . 171
6.3.6 DMA disable status register (DDIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
6.3.7 DMA restart register (DRST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
6.3.8 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) . . . . . . . . . . . . . . . . . . . . 173
6.4 DMA Bus States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
6.4.1 Types of bus states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
6.4.2 DMAC bus cycle state transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
6.5 Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
6.5.1 Single transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
6.5.2 Single-step transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
6.5.3 Block transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
6.6 Transfer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
6.6.1 Two-cycle transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
6.7 Transfer Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
6.7.1 Transfer type and transfer object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
6.8 DMA Channel Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
6.9 Next Address Setting Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
6.10 DMA Transfer Start Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
6.11 Forcible Interruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
6.12 DMA Transfer End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
6.12.1 DMA transfer end interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
6.12.2 Terminal count output upon DMA transfer end . . . . . . . . . . . . . . . . . . . . . . . . . . 182
6.13 Forcible Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
6.14 Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Chapter 7 Interrupt/Exception Processing Function . . . . . . . . . . . . . . . . . . . . . . . . . 183
7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
7.2 Non-Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
7.2.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
7.2.2 Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
7.2.3 Non-maskable interrupt status flag (NP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
7.2.4 Edge detection function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
8 Preliminary Users Manual U14913EE1V0UM00







D70F3123 equivalent, schematic
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Serial I/O Shift Registers 0, 1 (SIO0, SIO1) ............................................................. 351
Serial I/O Shift Registers L0, L1 (SIOL0, SIOL1) ..................................................... 352
Timing Chart in Single Transfer Mode (1/2) ............................................................. 353
Timing Chart According to Clock Phase Selection (1/2) ........................................... 355
Timing Chart of Interrupt Request Signal Output in Delay Mode (1/2) ..................... 357
Repeat Transfer (Receive-Only) Timing Chart ......................................................... 359
Repeat Transfer (Transmission/Reception) Timing Chart ........................................ 360
Timing Chart of Next Transfer Reservation Period ................................................... 361
Transfer Request Clear and Register Access Contention ........................................ 362
Interrupt Request and Register Access Contention ................................................. 363
Baud Rate Generators 0, 1 (BRG0, BRG1) Block Diagram ..................................... 365
Prescaler Mode Registers 0, 1 (PRSM0, PRSM1) ................................................... 366
Prescaler Compare Registers 0, 1 (PRSCM0, PRSCM1) ........................................ 367
Functional Blocks of the FCAN Interface .................................................................. 370
Memory Area of the FCAN System .......................................................................... 371
Clock Structure of the FCAN System ....................................................................... 380
FCAN Interrupt Bundling of V850E/CA1 (Atomic) .................................................... 381
Time Stamp Capturing at Message Reception ......................................................... 382
Time Stamp Capturing at Message Transmission .................................................... 383
16-Bit Data Write Operation for Specific Registers ................................................. 395
CAN Stop Register (CSTOP) .................................................................................. 396
CAN Main Clock Select Register (CGSC) (1/2) ........................................................ 397
Configuration of FCAN System Main Clock .............................................................. 398
Configuration of FCAN Global Time System Clock .................................................. 398
CAN Global Status Register (CGST) (1/2) ............................................................ 399
CAN Global Interrupt Enable Register (CGIE) (1/2) ............................................... 401
CAN Timer Event Enable Register (CGTEN) ......................................................... 403
CAN Global Time System Counter and event generation ........................................ 403
CAN Global Time System Counter (CGTSC) .......................................................... 404
CAN Message Search Start Register (CGMSS) ..................................................... 405
CAN Message Search Start Register (CGMSS) ..................................................... 406
CAN Test Bus Register (CTBR) .............................................................................. 407
Internal CAN Test Bus Structure .............................................................................. 407
CAN Interrupt Pending Register (CCINTP) ............................................................. 408
CAN Global Interrupt Pending Register (CGINTP) (1/2) ........................................ 409
CAN 1 to 3 Interrupt Pending Registers (C1INTP to C3INTP) (1/2) ....................... 411
Message Identifier Registers L00 to L63 and H00 to H63
(M_IDL00 to M_IDL63, M_IDH00 to M_IDH63) ...................................................... 413
Message Configuration Registers 00 to 63 (M_CONF00 to M_CONF63) ............... 414
Message Status Registers 00 to 63 (M_STAT00 to M_STAT63) ............................ 415
Message Set/Clear Status Registers 00 to 63 (SC_STAT00 to SC_STAT63) ........ 417
Message Data Registers m0 to m7 (M_DATAm0 to M_DATAm7) (m = 00 to 63) .. 418
Message Data Length Code Registers 00 to 63 (M_DLC00 to M_DLC63) ............. 420
Message Control Registers 00 to 63 (M_CTRL00 to M_CTRL63) (1/2) .................. 421
Message Time Stamp Registers 00 to 63 (M_TIME00 to M_TIME63) ..................... 423
Message Event Registers m0, m1, and m3
(M_EVTm0, M_EVTm1, M_EVm3) (m = 00 to 63) .................................................. 424
CAN 1 to 3 Mask 0 to 3 Registers L, H
(CxMASKL0 to CxMASKL3, CxMASKH0 to CxMASKH3) (x = 1 to 3) ................... 425
CAN 1 to 3 Control Registers (C1CTRL to C3CTRL) (1/4) ................................... 427
CAN 1 to 3 Definition Registers (C1DEF to C3DEF) (1/3) .................................... 431
CAN 1 to 3 Information Registers (C1LAST to C3LAST) ........................................ 434
CAN 1 to 3 Error Counter Registers (C1ERC to C3ERC) ....................................... 435
CAN 1 to 3 Interrupt Enable Registers (C1IE to C3IE) (1/2) ................................. 436
CAN 1 to 3 Bus Activity Registers (C1BA to C3BA) (1/2) ........................................ 438
CAN 1 to 3 Bit Rate Prescaler Registers (C1BRP to C3BRP) (1/2) ........................ 440
CAN Bus Bit Timing .................................................................................................. 442
CAN 1 to 3 Synchronization Control Registers (C1SYNC to C3SYNC) (1/2)) ......... 443
16 Preliminary User’s Manual U14913EE1V0UM00










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