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PDF ( 数据手册 , 数据表 ) D78F9418

零件编号 D78F9418
描述 UPD78F9418
制造商 NEC
LOGO NEC LOGO 


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D78F9418 数据手册, 描述, 功能
PRELIMINARY PRODUCT INFORMATION
MOS INTEGRATED CIRCUIT
µPD78F9418
8-BIT SINGLE-CHIP MICROCONTROLLER
The µPD78F9418 is µPD789417 sub-series product (LCD driver) of the 78K/0S series.
This microcontroller features an 8-bit CPU, LCD controller/driver, I/O ports, timers, a serial interface, A/D
converters, a comparator, and interrupt control circuits.
The µPD78F9418 replaces the internal masked ROM of the µPD789415, µPD789416, and µPD789417 with flash
memory, which enables the writing/erasing of a program while the device is mounted on the board.
The functions of this microcontroller is described in the following user’s manuals. Refer to these manuals
when designing a system based on this microcontroller.
µPD789407 and µPD789417 Sub-Series User’s Manual : To be released soon
78K/0S Series User’s Manual, Instruction
: U11047E
FEATURES
• Pin-compatible with masked ROM product (other than VPP pin)
• Flash memory: 32 Kbytes
• Internal data memory
High-speed RAM: 512 bytes
RAM for LCD display data: 28 bytes
• Variable instruction execution time: From high-speed (0.4 µs with the main system clock running at 5.0 MHz) to
ultra-low speed (122 µs with the subsystem clock running at 32.768 kHz)
• 43 I/O ports
• Serial interface channel: Switchable between three-wire serial I/O and UART modes
• LCD controller/driver:
Up to 28 segment signal outputs
Up to 4 common signal outputs
Bias switchable between 1/2 and 1/3
• Seven A/D converters with an 10-bit resolution
• Six timers:
16-bit timer/counter
Two 8-bit timer/event counters
8-bit timer/counter
Clock timer
Watchdog timer
• Power supply voltage VDD: 1.8 to 5.5 V
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Document No. U12321EJ1V0PM00 (1st edition)
Date Published August 1997 J
Printed in Japan
©
1997







D78F9418 pdf, 数据表
µPD78F9418
ANI0-ANI6 : Analog Input
ASCK
: Asynchronous Serial Input
AVDD
: Analog Power Supply
AVREF
: Analog Reference Voltage
AVSS
: Analog Ground
BIAS
: LCD Power Supply Bias Control
CMPIN0 : Comparator Input
CMPREF0 : Comparator Reference
CMPTOUT0 : Comparator Output
COM0-COM3 : Common Output
CPT5
: Capture Trigger Input
INTP0-INTP3 : Interrupt from Peripherals
KR0-KR5 : Key Return
P00-P03 : Port 0
P20-P27 : Port 2
P40-P47 : Port 4
P50-P53 : Port 5
P60-P66 : Port 6
P80-P87 : Port 8
P90-P93 : Port 9
RESET : Reset
RxD : Receive Data
S0-S27 : Segment Output
SCK
: Serial Clock
SI : Serial Input
SO : Serial Output
TI0, TI1 : Timer Input
TO2, TO5 : Timer Output
TxD : Transmit Data
VDD0, VDD1 : Power Supply
VLC0-VLC2 : LCD Power Supply
VPP : Programming Power Supply
VSS0, VSS1 : Ground
X1, X2 : Crystal (Main System Clock)
XT1, XT2 : Crystal (Subsystem Clock)
8







D78F9418 equivalent, schematic
µPD78F9418
5. CPU ARCHITECTURE
5.1 Memory Space
The µPD78F9418 can each access up to 64 Kbytes of memory space. Figure 5-1 shows the memory map.
Figure 5-1. Memory Map
FFFFH
Special function register
256 × 8 bits
FF00H
FEFFH
Internal high-speed RAM
512 × 8 bits
FD00H
FCFFH
FA 1 C H
FA 1 B H
Data memory space
FA 0 0 H
F9FFH
8000H
7FFFH
Unusable
RAM space for LCD
display data
28 × 8 bits
Unusable
7FFFH
Program area
Program memory
space
Internal flash memory
32 768 × 8 bits
0000H
0080H
007FH
0040H
003FH
0024H
0023H
0000H
CALLT table area
Program area
Vector table area
16










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