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PDF ( 数据手册 , 数据表 ) QD15TL04

零件编号 QD15TL04
描述 TFT LCD Module
制造商 Quanta
LOGO Quanta LOGO 


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QD15TL04 数据手册, 描述, 功能
Quanta Display Inc
Prepared Date:
4/9/2004
Preliminary
Quanta Display Inc.
SPECIFICATION
Doc No. QD15TL04-01
REV.: 01
Issue Date: 1/12/2005
Page: 25 pages
(Include cover page)
Specification for TFT LCD Module
Model No.
QD15TL04 Rev. 02
Customer’s Approval
Date
By
Approved
By







QD15TL04 pdf, 数据表
Quanta Display Inc
5-2 Inverter driving
5-2.1 Backlight lifetime
The backlight system is an edge-lighting type with single CCFT (Cold Cathode
Fluorescent Tube).
The lifetime of the lamp are shown in the following table.
Parameter
Lamp life time
Symbol Min.
LL 20000
Typ.
-
Max.
-
Unit
Hour
Remark
[Note]
[Note] Lamp life time is defined as the time when X occurs in the continuous
operation under the condition of Ta = 25 and SDA data=00HEX
X Brightness becomes 50% of the original value under standard condition.
5-2.2 Recommended Operation Condition
Parameter
Symbol Min.
Typ
Max Unit
Inverter power supply
Vin 7.5
-
21 V
voltage
Base of Brightness
VBB 4.85 5.0 5.2 V
control voltage
Brightness control IC
VBC 4.5 5.0 5.5 V
supply voltage
Logic signals
SDA, SCL 0
5V
FPVEE
5-2.3 DC Electrical Conditions
Ta=25
Parameter
Symbol
Condition
Min. Typ Max Unit Remark
VIN supply current
IVin VIN=7.5V,VBB=5V - 450 585
VIN=21V,VBB=5V
200
-
300 mA Note
Brightness control IC IVbc VBC=4.5~5.5V
supply current
SDA
Input voltage
low
Vil
VBC=4.5~5.5V
SCL
Input voltage
high
Vih
VBC=4.5~5.5V
FPVEE
Input voltage
low
Input voltage
high
Vil
Vih
VIN=7.5~21V
VIN=7.5~21V
Note: Brightness control from minmum to maximum
-
-
0.7
VBC
0
3.0
-
-
-
-
-
200 uA
0.3
VBC
-
0.6
V
V
V
5.0 V







QD15TL04 equivalent, schematic
Quanta Display Inc
38 26 Standard timing ID1
39 27 Standard timing ID1
40 28 Standard timing ID2
41 29 Standard timing ID2
42 2A Standard timing ID3
43 2B Standard timing ID3
44 2C Standard timing ID4
45 2D Standard timing ID4
46 2E Standard timing ID5
47 2F Standard timing ID5
48 30 Standard timing ID6
49 31 Standard timing ID6
50 32 Standard timing ID7
51 33 Standard timing ID7
52 34 Standard timing ID8
53 35 Standard timing ID8
54 36 Pixel Clock/10,000 (LSB)
55 37 Pixel Clock/10,000 (MSB)
56 38 Horizontal Active
57 39 Horizontal Blanking (Thbp)
58 3A Horizontal Active/Horizontal Blanking (Thbp)
59 3B Vertical Active
60 3C Vertical Blanking (Tvbp)
61 3D Vertical active/Vertical blanking (Tvbp)
62 3E Horizontal Sync, Offset (Thfp)
63 3F Horizontal Sync, Pulse Width
64 40 Vertical Sync, Offset (Tvfp)/Sync Width
65 41 Horizontal Vertical Sync Offset/Width upper 2 bits
66 42 Horizontal Image Size
67 43 Vertical Image Size
68 44 Horizontal Image Size / Vertical Image Size
69 45 Horizontal Border
70 46 Vertical Border
Non-interlaced, Normal, no stereo, Separate sync, H/V
pol Negatives, DE only note: LSB is set to “1” if panel is
71 47 DE-timing only. H/V can be ignored.
72 48 Flag
73 49 Flag
74 4A Flag
75 4B Data Type Tag: Descriptor Defined by Manufacturer
76 4C Flag
77 4D Value = HSPWmin /2 (pixel clks)
78 4E Value = HSPWmax /2 (pixel clks)
79 4F Value = Thbpmin /2 (pixel clks)
80 50 Value = Thbpmax /2 (pixel clks)
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
BC
1B
00
A0
50
20
17
30
30
20
26
00
4B
CF
10
00
00
18
00
00
00
0F
00
08
00
2A
00
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
10111100
00011011
00000000
10100000
01010000
00100000
00010111
00110000
00110000
00100000
00100110
00000000
01001011
11001111
00010000
00000000
00000000
00011000
00000000
00000000
00000000
00001111
00000000
00001000
00000000
00101010
00000000










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