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PDF ( 数据手册 , 数据表 ) A3S56D30GTP

零件编号 A3S56D30GTP
描述 256M Double Data Rate Synchronous DRAM
制造商 Zentel
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A3S56D30GTP 数据手册, 描述, 功能
A3S56D30GTP
A3S56D40GTP
256M Double Data Rate Synchronous DRAM
256Mb DDR SDRAM Specification
A3S56D30GTP
A3S56D40GTP
Zentel Electronics Corp.
Revision 1.1
Jul., 2013







A3S56D30GTP pdf, 数据表
A3S56D30GTP
A3S56D40GTP
256M Double Data Rate Synchronous DRAM
Burst Terminate (TERM) [/CS = L, /RAS = H, /CAS = H, /WE = L]
TERM command is used to truncate read bursts (with auto precharge disabled).
The most recently registered READ command prior to the TERM command will be truncated.
Precharge (PRE) [/CS = L, /RAS = L, /CAS = H, /WE = L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst
read / write operation. When A10 = H at this command, all banks are deactivated
(Precharge All Banks, PREA ). PRE command is treated as a NOP command if there is no open row
in that bank, or if the previously open row is already in the process of precharging.
Auto Refresh (REFA) [/CS = L, /RAS = L, /CAS = L, /WE = H, CKE =H]
REFA command starts Auto Refresh cycle. Refresh addresses including bank addresses are generated
internally. After REFA command, the banks are precharged automatically. Only DESEL or NOP
command is allowed within a period of tRFC from REFA command. The DDR SDRAM requires
Auto Refresh cycles at an average periodic interval of tREFI (maximum), with some flexibility that
a maximum of eight Auto Refresh commands can be posted and the maximum absolute interval
between any Auto Refresh command and the next Auto Refresh command is 8*tREFI.
Self Refresh (REFS) [/CS = L, /RAS = L, /CAS = L, /WE = H, CKE =L]
REFS command starts Self Refresh. When in the Self Refresh mode, the DDR SDRAM retains data
without external clocking. The DLL is automatically disabled upon entering Self Refresh, and is
automatically enabled upon exiting Self Refresh. Input signals except CKE are “Don’t Care” during
Self Refresh. Since CKE is an SSTL_2 input, VREF must be maintained during Self Refresh.
Revision 1.1
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Jul., 2013







A3S56D30GTP equivalent, schematic
A3S56D30GTP
A3S56D40GTP
256M Double Data Rate Synchronous DRAM
Power Up& Initialization Sequence
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other
than those specified may result in undefined operation.
1. Apply VDD before or with VDDQ such that VDDQ < VDD+0.3V.
2. Apply VDDQ before or with VTT & VREF such that VTT < VDDQ+0.3V & VREF < VDDQ+0.3V.
3. During power up, maintain an LVCMOS LOW level on CKE to keep DQ & DQS in the High-Z state.
4. After all power supply and reference voltages are stable, and CLK are stable, the DDR SDRAM
requires a 200us delay prior to applying an executable command.
5. CKE should be brought HIGH while keeping NOP or DESEL command.
6. Issue a PRECHARGE ALL command.
7. Issue an MRS command for the Extended Mode Register to enable the DLL.
8. Issue an MRS command for the Mode Register to reset the DLL and to program the operating parameters.
9. Maintain stable condition for 200 cycles for the DLL to lock.
10. Issue a PRECHARGE ALL command.
11. Once in the idle state, issue two AUTO REFRESH commands.
12. An MRS command for the Mode Register for programming the operating parameters
with DLL reset bit deactivated may be followed.
Following these cycles, the DDR SDRAM is idle and ready for normal operation.
Mode Register
Burst Length, Burst Type and CAS Latency can be programmed by CLK
setting the mode register. The mode register stores these data until the
next MRS command for the mode register, which may be issued when
all banks are in idle state. The DLL is reset by setting A8 of the mode
/CLK
/CS
register to one with A6-A0 set to the desired values. After tMRD from /RAS
an MRS command for the mode register, the DDR SDRAM is ready for /CAS
a new command other than READ or READA. READ or READA
command can be issued after 200 stable clock cycles from the MRS
/WE
command with DLL reset.
BA0
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
BA1
0 0 0 0 0 0 DR 0 LTMODE BT
BL
A12-A0
V
Latency
Mode
CL
000
001
010
011
100
101
110
111
CAS Latency
R
R
2
3
R
R
2.5
R
DLL Reset
0
1
NO
YES
Burst
Length
BL
000
001
010
011
100
101
110
111
BT=0
R
2
4
8
R
R
R
R
BT=1
R
2
4
8
R
R
R
R
Burst Type
0
1
Sequential
Interleaved
R: Reserved for Future Use
Revision 1.1
Page 15 / 40
Jul., 2013










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