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零件编号 | A3S64D40GTP | ||
描述 | 64M Double Data Rate Synchronous DRAM | ||
制造商 | Zentel | ||
LOGO | |||
1 Page
A3S64D40GTP
64M Double Data Rate Synchronous DRAM
64Mb DDR SDRAM Specification
A3S64D40GTP
Zentel Electronics Corp.
Revision 1.0
Nov., 2012
A3S64D40GTP
64M Double Data Rate Synchronous DRAM
COMMAND TRUTH TABLE
COMMAND
Deselect
No Operation
Row Address Entry &
Bank Active
Single Bank Precharge
Precharge All Banks
Column Address Entry
& Write
Column Address Entry
& Write with
Auto Precharge
Column Address Entry
& Read
Column Address Entry
& Read with
Auto Precharge
Auto Refresh
Self Refresh Entry
Self Refresh Exit
Burst Terminate
Mode Register Set
MNEMONIC CKE
n-1
DESEL
H
NOP
H
CKE
n
X
X
/CS
H
L
ACT
HHL
PRE
PREA
HHL
HHL
WRITE
HHL
WRITEA H H L
READ
HHL
READA
REFA
REFS
REFSX
TERM
MRS
HHL
HHL
HL L
L HH
L HL
HHL
HHL
/RAS
X
H
/CAS
X
H
/WE BA0, 1 A10
/AP
XXX
HXX
A0-9, note
11
X
X
L HHVVV
L HL VL X
L HL XHX
HL L VL V
HL L VHV
HL HVL V
HL HVHV
L L HXXX
L L HXXX
XXXXXX
HHHXXX
H H L X X X1
L L L L L V2
H=HIGH Level, L=LOW Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. Applies only to read bursts with autoprecharge disabled; this command is undefined (and should not be used) for
read bursts with autoprecharge enabled, and for write bursts.
2. BA0-BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register;
BA0 = 1, BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved;
A0-A11 provide the op-code to be written to the selected Mode Register.
Revision 1.0
Page 7/ 39
Nov., 2012
A3S64D40GTP
64M Double Data Rate Synchronous DRAM
EXTENDED MODE REGISTER
DLL enable/disable mode and drive strength for DQ/DQS output
buffers can be programmed by setting the extended mode register. The
extended mode register stores these data until the next MRS command for
the extended mode register, which may be issued when all banks are in
idle state. After tMRD from an MRS command for the extended mode
register, the DDR SDRAM is ready for a new command.
CLK
/CLK
/CS
/RAS
/CAS
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 1 0 0 0 0 0 0 0 0 0 0 DS DD
/WE
BA0
BA1
A11-A0
V
DLL Disable
Drive
Strength
0
1
0 DLL Enable
1 DLL Disable
Normal
Weak
Revision 1.0
Page 15/ 39
Nov., 2012
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页数 | 30 页 | ||
下载 | [ A3S64D40GTP.PDF 数据手册 ] |
零件编号 | 描述 | 制造商 |
A3S64D40GTP | 64M Double Data Rate Synchronous DRAM | Zentel |
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