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零件编号 | NB6L14S | ||
描述 | 2.5V 1:4 AnyLevel Differential Input to LVDS Fanout Buffer/Translator | ||
制造商 | ON Semiconductor | ||
LOGO | |||
1 Page
NB6L14S
2.5 V 1:4 AnyLevel]
Differential Input to LVDS
Fanout Buffer/Translator
The NB6L14S is a differential 1:4 Clock or Data Receiver and will
accept AnyLevel differential input signals: LVPECL, CML, LVDS, or
HSCL. These signals will be translated to LVDS and four identical
copies of Clock or Data will be distributed, operating up to 2.0 GHz or
2.5 Gb/s, respectively. As such, the NB6L14S is ideal for SONET,
GigE, Fiber Channel, Backplane and other Clock or Data distribution
applications.
The NB6L14S has a wide input common mode range from
GND + 50 mV to VCC − 50 mV. Combined with the 50 W internal
termination resistors at the inputs, the NB6L14S is ideal for translating
a variety of differential or single−ended Clock or Data signals to
350 mV typical LVDS output levels.
The NB6L14S is the 2.5 V version of the NB6N14S and is offered in
a small 3 mm x 3 mm 16−QFN package. Application notes, models,
and support documentation are available at www.onsemi.com.
The NB6L14S is a member of the ECLinPS MAX™ family of high
performance products.
Features
• Maximum Input Clock Frequency > 2.0 GHz
• Maximum Input Data Rate > 2.5 Gb/s
• 1 ps Maximum of RMS Clock Jitter
• Typically 10 ps of Data Dependent Jitter
• 380 ps Typical Propagation Delay
• 120 ps Typical Rise and Fall Times
• Single Power Supply; VCC = 2.5 $ 5%
• VREF_AC Reference Output
• These are Pb−Free Devices
Device DDJ = 10 ps
http://onsemi.com
1
QFN−16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB6L
14S
ALYW G
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Q0
Q0
IN
VT
IN
50 W
50 W
EN
(LVTTL/CMOS)
VREFAC
DQ
Q1
Q1
Q2
Q2
Q3
Q3
Figure 1. Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
TIME (58 ps/div)
Figure 2. Typical Output Waveform at 2.488 Gb/s with
PRBS 223−1 (VINPP = 400 mV; Input Signal DDJ = 14 ps)
© Semiconductor Components Industries, LLC, 2011
October, 2011 − Rev. 2
1
Publication Order Number:
NB6L14S/D
VCC = 3.3 V or 2.5 V
VCC = 2.5 V
NB6L14S
VCC = 2.5 V
VCC = 2.5 V
HSTL
Driver
Zo = 50 W
VT = GND
Zo = 50 W
NB6L14S
IN
50 W
50 W
IN
GND
GND
Figure 14. HSTL Interface
VCC = 2.5 V
VCC = 2.5 V
LVCMOS
Driver
Zo = 50 W
VT = OPEN
2.5 kW
NB6L14S
IN
50 W*
50 W*
IN
GND
GND
GND
Figure 15. LVCMOS Interface
VCC
VCC = 2.5 V
LVTTL
Driver
GND
Zo = 50 W
VT = OPEN
1.5 kW
GND
NB6L14S
IN
50 W*
50 W*
IN
GND
Figure 16. LVTTL Interface
VCC
Differential
Driver
Zo = 50 W
VT = VREFAC*
Zo = 50 W
NB6L14S
IN
50 W
50 W
IN
GND
GND
Figure 17. Capacitor−Coupled Differential
Interface (VT Connected to VREF_AC)
*VREFAC bypassed to ground with a 0.1 mF capacitor.
VCC = 2.5 V
Single−Ended
Driver
Zo = 50 W
VT = VREFAC*
NB6L14S
IN
50 W
50 W
IN
GND
GND
Figure 18. Capacitor−Coupled Single−Ended Interface (VT Connected to VREFAC)
*VREFAC bypassed to ground with a 0.1 mF capacitor.
http://onsemi.com
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页数 | 11 页 | ||
下载 | [ NB6L14S.PDF 数据手册 ] |
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NB6L14S | 2.5V 1:4 AnyLevel Differential Input to LVDS Fanout Buffer/Translator | ON Semiconductor |
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