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PDF ( 数据手册 , 数据表 ) NB3M8T3910G

零件编号 NB3M8T3910G
描述 2.5V/3.3V 3:1:10 Configurable Differential Clock Fanout Buffer
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NB3M8T3910G 数据手册, 描述, 功能
NB3M8T3910G
2.5V/3.3V 3:1:10
Configurable Differential
Clock Fanout Buffer with
LVCMOS Reference Output
Description
The NB3M8T3910G is a 3:1:10 Clock fanout buffer operating on a
2.5 V/3.3 V Core VDD and a flexible 2.5 V / 3.3 V VDDO supply
(VDDO VDD).
A 3:1 MUX selects between Crystal oscillator inputs, or either of
two differential Clock inputs capable of accepting LVPECL, LVDS,
HCSL, or SSTL levels. The MUX select lines, SEL0 and SEL1, accept
LVCMOS or LVTTL levels and select input per Table 3. The Crystal
input is disabled when a Clock input is selected.
Differential Outputs consist of two banks of five differential outputs
with each bank independently mode configurable as LVPECL, LVDS
or HCSL. Each bank of differential output pairs is configured with a
pair of SMODEAx/Bx select lines using LVCMOS or LVTTL levels
per Table 6. Clock input levels and outputs states are determined per
Table 5.
The Single−Ended LVCMOS Output, REFOUT, is synchronously
enabled by the OE_SE control line per Table 4 using LVCMOS /
LVTTL levels. For Clock frequencies above 250 MHz, the REFOUT
line should be disabled.
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MARKING
DIAGRAM
1
1 48
QFN48
G SUFFIX
CASE 485AJ
NB3M8T
3910G
AWLYYWWG
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information on page 19 of
this data sheet.
Features
Crystal, Single−Ended or Differential Input Reference
Clocks
Differential Input Pair can Accept: LVPECL, LVDS,
HCSL, SSTL
Two Output Banks: Each has Five Differential Outputs
Configurable as LVPECL, LVDS, or HCSL by
SMODEAx/Bx Pins
One Single−Ended LVCMOS Output with Synchronous
OE Control
LVCMOS/LVTTL Interface Levels for all Control
Inputs
Clock Frequency: Up to 1400 MHz, Typical
Output Skew: 50 ps (Max)
Additive RMS Jitter <0.03 ps (156.25 MHz, Typical)
Input to Output Propagation Delay (900 ps Typical)
Operating Supply Modes VDD/VDDO: 2.5 V/2.5 V,
3.3 V/3.3 V or 3.3 V/2.5 V
Industrial Temperature Range −40°C to 85°C
This is a Pb−Free Device
Applications
Clock Distribution
Telecom
Networking
Backplane
High End Computing
Wireless and Wired Infrastructure
End Products
Servers
Ethernet Switch/Routers
ATE
Test and Measurement
© Semiconductor Components Industries, LLC, 2016
March, 2016 − Rev. 2
1
Publication Order Number:
NB3M8T3910/D







NB3M8T3910G pdf, 数据表
NB3M8T3910G
AC ELECTRICAL CHARACTERISTICS
Table 16. AC ELECTRICAL CHARACTERISTICS, VDD/VDDO = 2.5 V/2.5 V, 3.3 V/3.3 V or 3.3 V/2.5 V ±5%; GND = 0.0 V;
TA = −40°C to 85°C (Note 9)
Symbol
Parameter
Test Conditions
Min Typ Max Unit
fOSC
fOUT
Input Frequency
Output Frequency
External Crystal Input
Diff CLKx/CLKx Inputs
OUTPUTS: LVPECL
OUTPUTS: LVDS
OUTPUTS: HCSL
OUTPUTS: REFOUT
10 50 MHz
1400
1200
250
250
MHz
Single−ended Inputs
XTAL_IN, CLKx, or CLKx
250
tJITTERΦ
Buffer Additive RMS Phase Jitter
(Integrated 12 kHz − 20 MHz)
Diff CLKx/CLKx Inputs
Single ended XTAL_IN
0.03 ps
0.03
tPD Propagation Delay;
tsk(o)
Output−to−Output Skew
CLKx/CLKx to any Qx/Qx
Output Mode LVPECL
Output Mode LVDS
Output Mode HCSL
Output REFOUT, CL = 10 pF
Any Two Clock Outputs with the
Same Buffer Type and Same Load
700
850
950
1600
900
1100
1300
2000
25
1200
1400
1650
2600
50
ps
ps
tsk(pp)
Part−to−Part Skew;
Output Mode LVPECL
Output Mode LVDS
Output Mode HCSL
ps
45
30
30
TOD
Valid to High Z Delay, Output
CLKx/CLKx
Disable
200 ns
TOE
High Z to Valid Delay, Output
CLKx/CLKx
Enable
200 ns
VRB Ringback Voltage Margin
(Notes 10, 11)
HCSL Output
−100
100 mV
VMAX
VMIN
VCROSS
Voltage High (Notes 12, 13)
Voltage Low (Notes 12, 14)
Absolute Crossing Voltage
(Notes 12, 15, 16)
HCSL Output
HCSL Output
HCSL Output
520
−150
160
920 mV
150 mV
460 mV
DVCROSS
Total Variation of VCROSS over all
edges; (Notes 12, 15 and 17)
HCSL Output
140 mV
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed
circuit board with maintained transverse airflow greater than 500 lfpm.
9. OUTPUT MODE LVPECL: Output pairs are terminated with 50 W to VDDO − 2 V.
OUTPUT MODE LVDS: Output pairs are terminated with 100 W line to line at receiver.
OUTPUT MODE HCSL: Output pairs are terminated with 50 W to GND
REFOUT Output terminated with 50 W to VDDO/2.
10. Measurement taken from differential waveform.
11. TSTABLE is the time the differential clock must maintain a minimum ± 150 mV differential voltage after rising/falling edges before it is al-
lowed to drop back into the VRB ±100 mV differential range.
12. Measurement taken from single−ended waveform.
13. Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
14. Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
15. Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of Qx.
16. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement.
17. Defined as the total variation of all crossing voltages of rising Qx and falling nQx, This is the maximum allowed variance in Vcross for any
particular system.
18. Measured from −150 mV to +150 mV on the differential waveform (Qx minus nQx). The signal must be monotonic through the measure-
ment region for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing.
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8







NB3M8T3910G equivalent, schematic
NB3M8T3910G
Crystal Input Interface
The device has been characterized with 18 pF parallel
resonant crystals. The capacitor values, C1 and C2, shown
in Figure 23 below were determined using an 18 pF parallel
resonant crystal and were chosen to minimize the ppm error.
The C1 and C2 load caps are in parallel and must be reduced
by any input and stray capacitance. Typical value would be
36 pF minus all input and stray capacitance, or about 25 to
30 pF. The optimum C1 and C2 values can be slightly
adjusted for different board layouts.
CLOCK Overdriving the XTAL Interface
The XTAL_IN input can accept a single−ended LVCMOS
signal through an AC coupling capacitor. A general
LVCMOS interface diagram is shown in Figure 24 and a
general LVPECL interface in Figure 25. The XTAL_OUT
pin must be left floating. The maximum amplitude of the
input signal should not exceed 2 V and the input edge rate
can be as slow as 10 ns. This configuration requires that the
output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In
addition, matched termination at the crystal input will
attenuate the signal in half. This can be done in one of two
ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50 W applications,
R1 and R2 can be 100 W. This can also be accomplished by
removing R1 and making R2 50 W. By overdriving the
crystal oscillator, the device will be functional, but note, the
device performance is guaranteed by using a quartz crystal.
Figure 23. Crystal Input Interface
VDD
RO
LVCMOS
Rs
Z0 = RO + Rs
R1
100 W
Zo = 50 W
R2
100 W
XTAL_IN
C1
0.1 mF
XTAL_OUT
NB3M8T3910G
GND
Figure 24. General Diagram for LVCMOS Driver to XTAL Input Interface
LVPECL
Zo = 50 W
Zo = 50 W
R1
50 W
XTAL_IN
C1
0.1 mF
XTAL_OUT
R2
50 W
NB3M8T3910G
GND
Figure 25. General Diagram for LVPECL Driver to XTAL Input Interface
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16










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