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PDF ( 数据手册 , 数据表 ) NB3F8L3010C

零件编号 NB3F8L3010C
描述 3.3V / 2.5V / 1.8V / 1.5V 3:1:10 LVCMOS Fanout Buffer
制造商 ON Semiconductor
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NB3F8L3010C 数据手册, 描述, 功能
NB3F8L3010C
3.3V / 2.5V / 1.8V / 1.5V
3:1:10 LVCMOS Fanout Buffer
Description
The NB3F8L3010C is a 3:1:10 Clock / Data fanout buffer operating
on a 3.3 V / 2.5 V Core VDD and two flexible 3.3 V / 2.5 V / 1.8 V /
1.5 V VDDOn supplies which must be equal or less than VDD.
A Mux selects between a Crystal input, or either of two
differential/SE Clock / Data inputs. Differential Inputs accept
LVPECL, LVDS, HCSL, or SSTL and Single−Ended levels. The
MUX control lines, SEL0 and SEL1, select CLK0/CLK0,
CLK1/CLK1, or Crystal input pins per Table 3. The Crystal input is
disabled when a Clock input is selected. Output enable pin, OE,
synchronously forces a High Impedance state (HZ) when Low per
Table 4.
Outputs consist of 10 single−ended LVCMOS outputs.
Features
Ten CMOS / LVTTL Outputs up to 200 MHz
Differential Inputs Accept LVPECL, LVDS, HCSL, or SSTL
Crystal Oscillator Interface
Crystal Input Frequency Range: 10 MHz to 50 MHz
Output Skew: 10 ps Typical
Additive RMS Phase Jitter @ 125 MHz, (12 kHz – 20 MHz): 0.03 ps
(Typical)
Synchronous Output Enable
Output Defined Level When Input is Floating
Power Supply Modes:
Single 3.3 V
Single 2.5 V
Mixed 3.3 V ± 5% Core/2.5 V ± 5% Output Operating Supply
Mixed 3.3 V ± 5% Core/1.8 V ± 0.2 V Output Operating Supply
Mixed 3.3 V ± 5% Core/1.5 V ± 0.15 V Output Operating Supply
Mixed 2.5 V ± 5% Core/ 1.8 V ± 0.2 V Output Operating Supply
Mixed 2.5 V ± 5% Core /1.5 V ± 0.15 V Output Operating Supply
Two Separate Output Bank Power Supplies
Industrial temp. range -40°C to 85°C
These are Pb−Free Devices
Applications
Clock Distribution
Networking and Communications
High End Computing
Wireless and Wired Infrastructure
End Products
Servers
Ethernet Switch/Routers
ATE
Test and Measurement
www.onsemi.com
1 32
QFN32
G SUFFIX
CASE 488AM
MARKING
DIAGRAM
1
NB3F8L
3010C
AWLYYWWG
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information page 12 of this
data sheet.
© Semiconductor Components Industries, LLC, 2016
May, 2016 − Rev. 7
1
Publication Order Number:
NB3F8L3010C/D







NB3F8L3010C pdf, 数据表
NB3F8L3010C
PARAMETER MEASUREMENT INFORMATION
VDD
CLK
CLK
GND
VPP
Xpoint
Differential Input Level
VCMR
Qx
Qv
VDDOn/2
VDDOn/2
tsk(0)
Within Device Output Skew
OE
Qx
Qx
VDD
VDD/2
tEN tDIS
VDDOn/2
0V
VOH
VDDOn/2VOL
VDDOn/2
Qx
tPW
tPeriod
odc = (tPW / tPeriod) x 100%
Output Enable /Disable
(OE HIGH = Enabled)
20%
tR
80%
80%
tF
20%
Output Duty Cycle / Pulse Width / Period
Spectrum of Output Signal Qx
A0
MUX  _ISOL = A0 - A1
A1
MUX selects
active inpu t clock
signal
MUX selects
static input
Output Rise/Fall Time
Frequ ency (Hz)
fc
(Fundamental)
MUX Isolation
Figure 4. Operational Waveforms and MUX Input Isolation Plot
APPLICATION INFORMATION
Recommendations for Unused LVCMOS Output Pins
Inputs:
CLK/CLK Inputs
For applications not requiring the use of the differential
input, both CLK and CLK can be left floating. Though not
required, but for additional protection, a 1 kW resistor can be
tied from CLK to ground.
Crystal Inputs
For applications not requiring the use of the crystal
oscillator input, both XTAL_IN and XTAL_OUT can be left
floating. Though not required, but for additional protection,
a 1 kW resistor can be tied from XTAL_IN to ground.
LVCMOS Control Pins
All control pins have internal pulldowns; additional
resistance is not required but can be added for additional
protection. A 1 kW resistor can be used.
Power Supplies
VDD is the power supply for the core and input circuitry.
VDDOA and VDDOB are two separate positive power
supplies for two banks of outputs:
VDDOA pins 2 and 6 are connected internally for outputs
Q0 − Q4.
VDDOB pins 19 and 23 are connected internally for outputs
Q5 − Q9.
LVCMOS Outputs
A 33 W series terminating resistor may be used on each
clock output if the trace is longer than 1 inch.
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