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PDF ( 数据手册 , 数据表 ) MT90810AK3

零件编号 MT90810AK3
描述 Flexible MVIP Interface Circuit
制造商 Zarlink Semiconductor
LOGO Zarlink Semiconductor LOGO 


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MT90810AK3 数据手册, 描述, 功能
CMOS MT90810
Flexible MVIP Interface Circuit
Data Sheet
Features
• MVIPand ST-BUScompliant
• MVIP Enhanced Switching with 384x384 channel
capacity (256 MVIP channels; 128 local
channels)
• On-chip PLL for MVIP master/slave operation
• Local output clocks of 2.048,4.096,8.192 MHz
with programmable polarity
• Local serial interface is programmable to 2.048,
4.096 or 8.192 Mb/s with associated clock
outputs
• Additional control output stream
• Per-channel message mode
• Two independently programmable groups of up to
12 framing signals each
• Motorola non-multiplexed or Intel
multiplexed/non-multiplexed microprocessor
interface
Applications
• Medium size digital switch matrices
• MVIP interface functions
• Serial bus control and monitoring
August 2005
Ordering Information
MT90810AK3 100 Pin PQFP*
*Pb Free Sn-Bi Plating
Trays
0°C to +70°C
• Centralized voice processing systems
• Voice/Data multiplexer
Description
Zarlink’s MT90810 is a Flexible MVIP Interface Circuit
(FMIC). The MVIP (Multi-Vendor Integration Protocol)
compliant device provides a complete MVIP compliant
interface between the MVIP Bus and a wide variety of
processors, telephony interfaces and other circuits. A
built-in digital time-slot switch provides MVIP enhanced
switching between the full MVIP Bus and any
combination of up to 128 full duplex local channels of
64 kbps each. An 8 bit microprocessor port allows real-
time control of switching and programming of device
configuration. On-board clock circuitry, including both
analog and digital phase-locked loops, supports all
MVIP clock modes. The local interface supports PCM
rates of 2.048, 4.096 and 8.192 Mb/s, as well as
parallel DMA through the microprocessor port.
SEC8K
C4b
C2o
F0b
DSo[0:7]
DSi[0:7]
LDO[0:3]
LDI[0:3]
TCK
TMS
TDI
TDO
EX_8KA EX_8KB X2 X1/CLKIN PLL_LO PLL_LI FRAME
Timing and Clock Control
(Oscillator and Analog & Digital PLLs)
Enhanced Switch
S-P/ Data Memory
P-S
Connection Memory
Programmable
Framing Signals
JTAG
Microprocessor Interface
CLK2
CLK4
CLK8
RESET
CSTo
FGA[0:11]
FGB[0:11]
ERR
AD[0:7] A[0:1] ALE WR/ RD/ CS RDY/ DREQ[0:1] DACK[0:1]
R/W DS
DTACK
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Reserved.







MT90810AK3 pdf, 数据表
MT90810
Data Sheet
EX_8KA
EX_8KB
C4b
X2
External
16MHz Crystal
X1
F0b
div 4
div 2
SEC8K
1, 5
2, 6 PLL_MODE
3, 7
Digital
PLL
EX_8KA
EX_8KB
0
SEL_S8K
1
SEC8K
16MHz
4
0
PLL_MODE
(sampler)
Jittery 4.096MHz
60ns peak jitter
FRAME
4.096MHz
2 EN_SEC8K
Analog PLL
Phase
up/
PLL_LO
XCLK_SEL
0
2
1
Comparator down
div 4
16MHz div VCO
by 2 @32MHz
external
loop
filter
External 8kHz
8kHz
FRAME
PLL_LI
FMIC
state
machine
F0b
CLK8
C4b
CLK4
C2o
CLK2
Figure 4 - Clock Control Functional Block Diagram
The operation of the PLLs and the state machine is controlled by the clock control register as described in Figure 6
- “Clock Control (CLK_CNTRL) Register” and Tables 8 to 10. The clock circuitry (PLLs and state machine) operates
in eight different modes.
1. FMIC as Timing Master (Mode 0)
The FMIC is configured as the timing master (CLK_CNTRL register cleared, PLL mode 0 selected) after reset. The
external 16.384 MHz input is divided by four and used as the input to the analog PLL so the internal master clock is
phase locked to the 16.384 MHz oscillator. The FMIC state machine is free-running and does not synchronize to
any external 8 kHz source.
In this mode, the XLCK_SEL bits of the clock control register can be programmed to accommodate an 8.192 MHz
or 4.096 MHz external clock instead of the default 16.384 MHz.
The FMIC becomes MVIP master when MVIP_MST bit is set in the Control/Status register. This mode can be used
when the FMIC chip is to become timing master in a system which has no digital network connections (T1 or E1).
2. FMIC as MVIP Slave (Mode 4)
When this mode is selected, MVIP C4 clock is selected as the input to the analog PLL. The FMIC internal master
clock is then synchronized to the MVIP bus timing. The FMIC state machine is also synchronized to the MVIP F0
framing signal.
The MVIP_MST bit in the Control/Status register should never be set when the device is in mode 4 as the FMIC is
entirely slave to the MVIP bus timing.
3. FMIC as MVIP Master (Mode 1,2,3)
In modes 1 through 3, the output of the device’s digital PLL is selected as the input to the analog PLL. The source
to the digital PLL is selected as either SEC8K, EX_8KA or EX_8KB depending on the particular mode (1, 2 or 3)
chosen.
In these modes, the FMIC state machine is not synchronized to the external 8 kHz input selected, that is, the state
machine output 8 kHz FRAME and F0b signals may not be phase aligned with the external 8 kHz input but will
always be frequency locked.
8
Zarlink Semiconductor Inc.







MT90810AK3 equivalent, schematic
MT90810
Data Sheet
EN_SEC8K
SEL_S8K
PLL_MODE XCLK_SEL
76543210
Figure 6 - Clock Control (CLK_CNTRL) Register
Name
SEL_S8K
EN_SEC8K
Description
Mode [bits]
Function
Selects source of 8kHz signal driven out on SEC8K pin
0 [00]
Select EX_8KA as SEC8K output
1 [01]
Select EX_8KB as SEC8K output
2 [10]
Select FRAME as SEC8K output
3 [11]
RESERVED
Enables SEC8K as output
Table 8 - EN_SEC8K and SEL_S8K Bits
Mode
[bits]
0 [000]
1 [001]
2 [010]
3 [011]
4 [100]
Description
APLL source Frame Sync.
Function
X1 divided by
1,2, or 4
no frame
sync.
FMIC as Timing Master
• FMIC defaults to this mode after reset (Clock Control Register
is cleared).
• X1 divided by 1,2 or 4 is used as the input to the APLL.
• State machine is free running and does not synchronize to any
external 8 kHz source.
• XCLK_SEL can be programmed to any mode.
• MVIP_MST bit in MCS is set.
• Used when the FMIC is to become the timing master in a
system which has no digital network connections (T1 or E1).
SEC8K >DPLL
EX8KA >DPLL
EX8KB >DPLL
no frame
sync.
FMIC as MVIP Master (Slaved to external 8 kHz)
• DPLL is selected as the source to the APLL. Input to the DPLL
is either SEC8K,EX8KA/EX8KB.
• State machine is not synchronized to external 8 kHz
(SEC8K/EX8KA/B); that is, FRAME signal is freq locked but not
necessarily phase aligned with external 8 kHz.
• XCLK_SEL must be programmed to mode 0.
• MVIP_MST bit in MCS is set.
MVIP C4
frame sync.
to F0
FMIC as MVIP Slave
• FMIC is entirely slaved to MVIP bus timing.
• MVIP C4 is selected as input to APLL.
• State machine is synchronized to MVIP C4 and F0 inputs.
• MVIP_MST bit in MCS register must be cleared.
Table 9 - PLL_MODE Bits (control PLL and frame synchronization)
16
Zarlink Semiconductor Inc.










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