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PDF ( 数据手册 , 数据表 ) STD24N06L

零件编号 STD24N06L
描述 Power MOSFET ( Transistor )
制造商 ON Semiconductor
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STD24N06L 数据手册, 描述, 功能
NTD24N06L, STD24N06L
Power MOSFET
24 A, 60 V, Logic Level, N−Channel DPAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
Features
S Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
Typical Applications
Power Supplies
Converters
Power Motor Controls
Bridge Circuits
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol Value
Unit
Drain−to−Source Voltage
Drain−to−Gate Voltage (RGS = 10 MW)
Gate−to−Source Voltage
− Continuous
− Non−repetitive (tpv10 ms)
Drain Current
− Continuous @ TA = 25°C
− Continuous @ TA = 100°C
− Single Pulse (tpv10 ms)
Total Power Dissipation @ TA = 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (Note 1)
Total Power Dissipation @ TA = 25°C (Note 2)
Operating and Storage Temperature Range
VDSS
VDGR
VGS
VGS
ID
ID
IDM
PD
TJ, Tstg
60
60
"15
"20
24
10
72
62.5
0.42
1.88
1.36
−55 to
+175
Vdc
Vdc
Vdc
Adc
Apk
W
W/°C
W
W
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 5.0 Vdc,
L = 1.0 mH, IL(pk) = 18 A, VDS = 60 Vdc)
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
Maximum Lead Temperature for Soldering
Purposes, 1/8 in from case for 10 seconds
EAS 162 mJ
RqJC
RqJA
RqJA
TL
°C/W
2.4
80
110
260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. When surface mounted to an FR4 board using 0.5 sq. in. pad size.
2. When surface mounted to an FR4 board using minimum recommended pad
size.
http://onsemi.com
24 AMPERES, 60 VOLTS
RDS(on) = 0.036 W (Typ)
D
N−Channel
G
S
4
12
3
DPAK
CASE 369C
(Surface Mount)
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
1
Gate
2
Drain
3
Source
A
Y
WW
24N6L
G
= Assembly Location*
= Year
= Work Week
= Device Code
= Pb−Free Package
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 4
1
Publication Order Number:
NTD24N06L/D












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